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VerilogHDL
本书简要介绍了Verilog硬件描述语言的基础知识，包括语言的基本内容和基本结构 ，以及利用该语言在各种层次上对数字系统的建模方法。书中列举了大量实例，帮助读者掌握语言本身和建模方法，对实际数字系统设计也很有帮助。本书是Verilog HDL的初级读本，适用于作为计算机、电子、电气及自控等专业相关课程的教材，也可供有关的科研人员作为参考书。(This book briefly introduces the Verilog hardware description language basics, including basic elements of language and basic structure, and the use of the language at various levels on the digital system modeling. The book lists a large number of examples to help readers master the language itself and the modeling of the actual digital system design is also helpful. Verilog HDL book is a primer for a computer, electronic, electrical and automatic control and other specialized courses related to materials, but also for the researchers as a reference.)
- 2010-05-11 19:54:29下载
- 积分：1
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eda
EDA 正弦信号发生器：正弦信号发生器的结构有四部分组成，如图1所示。20MHZ经锁相环PLL20输出一路倍频的32MHZ片内时钟,16位计数器或分频器CNT6，6位计数器或地址发生器CN6，正弦波数据存储器data_rom。另外还需D/A0832（图中未画出）将数字信号转化为模拟信号。此设计中利用锁相环PLL20输入频率为20MHZ的时钟，输出一路分频的频率为32MHZ的片内时钟，与直接来自外部的时钟相比，这种片内时钟可以减少时钟延时和时钟变形，以减少片外干扰 还可以改善时钟的建立时间和保持时间，是系统稳定工作的保证。CNT6用来将32MHZ进行8分频得到4096HZ的频率提供给CN6与data_rom时钟信号。由CLK端输入20MHZ的时钟信号，在DOUT端就可输出稳定的正弦信号。(Sine signal generator has the structure of four parts, as shown in figure 1 below. The 20 MHZ phase lock loop PLL20 output all the way of frequency doubled within 32 MHZ slice clock, 16 counter or prescaler CNT6, six counter or address generator CN6, sine data storage data_rom. In addition to D/A0832 (shown in not draw) will digital signal into analog signals. This design using the phase lock loop PLL20 input frequency for 20 MHZ clock, the output of the frequency of all points frequency of 32 pieces (MHZ clock, and comes directly from the external clock, compared to this piece of clock can reduce the clock in delay and clock deformation, to reduce the interference of Can also improve the establishment of the clock time and keep time, is the system stability of assurance. CNT6 used to will and to 8 MHZ get 4096 HZ dividing the frequency to provide CN6 and data_rom clock signal. The input by CLK 20 MHZ clock signal, in DOUT end can output stable sine signals.
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- 2021-03-07 15:49:29下载
- 积分：1
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学习Xilinx公司开发软件ISE的基础资料，从最基础到复杂逻辑设计。
学习Xilinx公司开发软件ISE的基础资料，从最基础到复杂逻辑设计。-Learning Xilinx software ISE developed the basis of information from the most basic to complex logic design.
- 2022-05-27 10:26:09下载
- 积分：1
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本程序是用VHDL语言实现电子密码锁功能,整个系统分为三大模块,一为控制模块,二为键盘显示模块,三为处理模块...
本程序是用VHDL语言实现电子密码锁功能,整个系统分为三大模块,一为控制模块,二为键盘显示模块,三为处理模块-This procedure is a VHDL language electronic code lock function, the entire system is divided into three modules, one for the control module, two for the keyboard display module, three modules for the treatment
- 2022-05-08 19:29:46下载
- 积分：1
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FM
说明： 基于FPGA和弦！！！音乐芯片的设计与实现！！！(Design and implementation of FPGA chip based on the chord music)
- 2015-01-07 17:02:29下载
- 积分：1
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利用VHDL语言设计一个分频器，输入为CLK,输出分别为CLK1、CLK8、CLK256、 CLK1024...
利用VHDL语言设计一个分频器，输入为CLK,输出分别为CLK1、CLK8、CLK256、 CLK1024-The use of VHDL language design a divider, input CLK, the output respectively, CLK1, CLK8, CLK256, CLK1024
- 2022-06-02 16:58:00下载
- 积分：1
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N-bits-by-M-bits
这是一个verilog代码实现的常用乘法器。设计的是通用N比特乘M比特的二进制乘法器(This is a common multiplier verilog code. Design of a generic N bits by M bits of the binary multiplier)
- 2013-10-05 19:44:52下载
- 积分：1
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can_exm1_sys
CAN总线的数据采集，FPGA到USB。verilog hdl语言。(CAN bus data acquisition, FPGA to the USB. verilog hdl language.)
- 2013-05-31 15:01:11下载
- 积分：1
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数字计时器，使用VHDL语言编写，使用数码管显示，精确到ms
数字计时器，使用VHDL语言编写，使用数码管显示，精确到ms-digital timer, the use of VHDL development, the use of digital control, the precision of the ms
- 2022-05-20 00:23:22下载
- 积分：1
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VHDL显示六位学好
在八位七段数码显示管上显示8位学号，要显示的学号可以在程序内改，经设备验证无错误，且运行良好。
- 2022-05-30 18:34:23下载
- 积分：1
