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DI-S-AND-V
这个程序是为了区分SIGNAL和VARIABLE在不同情况下要怎样使用的例程,程序中使用了三种情况来说明问题(This program is designed to differentiate between routine SIGNAL VARIABLE in different situations and how you want to use, the program uses the three cases to illustrate the problem
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- 2015-01-12 12:56:26下载
- 积分:1
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JESD204B_character
JESD204协议简单透彻的讲解,对做高速AD的朋友有一定的帮助(Understanding control characters in JESD204)
- 2014-10-11 16:17:23下载
- 积分:1
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一些简单的VHDL实例,主要是介绍一些基本逻辑们及一些组合、时序电路的例子,供大家参考...
一些简单的VHDL实例,主要是介绍一些基本逻辑们及一些组合、时序电路的例子,供大家参考-Some simple examples of VHDL, mainly to introduce some basic logic and some combination of sequential circuit examples for your reference
- 2022-01-31 04:35:55下载
- 积分:1
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VGA显示彩色图像,VHDL,Quartus
vga显示彩色图像ip,alter开发板-vga display color image,vhdl,quartus
- 2022-09-20 17:40:02下载
- 积分:1
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一种基于LUT的预失真方法。其中的一部分,有参考价值。
一种基于LUT的预失真方法。其中的一部分,有参考价值。-one method of DPD based on LUT
- 2022-06-30 17:35:36下载
- 积分:1
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六个数码码动态扫描接口程序,用VERILOG语言编写的
六个数码码动态扫描接口程序,用VERILOG语言编写的-Six digital code dynamic scan interface program, using Verilog language
- 2022-03-24 21:40:23下载
- 积分:1
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Based on the VHDL language for selecting the three sequences, you can have a cyc...
基于VHDL语言的3级序列的产生,可以循环产生周期为7的m序列
-Based on the VHDL language for selecting the three sequences, you can have a cycle for cycle 7 m sequence
- 2023-08-16 17:00:04下载
- 积分:1
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位同步例程源代码,FPGA应用领域,Verilog
位同步例程源代码,FPGA应用领域,Verilog-Bit synchronization routines source code, FPGA applications, Verilog
- 2022-03-25 15:19:48下载
- 积分:1
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循环冗余校验码(试验报告)
循环冗余校验码(试验报告)-Cyclic Redundancy Check (pilot reports)
- 2022-03-18 10:59:43下载
- 积分:1
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super fast debounce button on vhdl, xilinx xc
super fast debounce button on vhdl, xilinx xc
- 2022-10-30 03:20:04下载
- 积分:1