-
基于fpga的DDS程序 AD9767
基于fpga的DDS程序 可输出正弦波 方波 三角波 锯齿波(DDS program based on FPGA can output sinusoidal square wave triangular wave sawtooth wave)
- 2020-06-20 21:00:01下载
- 积分：1
-
USB2.0的IP核（详细verilog源码和文档）
USB2.0的IP核开发.代码可以直接使用已经验证过(USB2.0 IP kernel development. Code can be used directly, has been verified)
- 2020-12-24 18:49:04下载
- 积分：1
-
Booth2_final
该文件是booth乘法器的verilog源代码，经过最终的仿真，可以直接运行(This file is booth multiplier verilog code, after the final simulation, can be directly run)
- 2015-05-08 09:29:56下载
- 积分：1
-
宝宝挂
最新热血江湖外挂，需要的可以下载，游戏开心热血江湖应用辅助(Yulgang latest plug-in needed to download, games happy))
- 2020-06-23 09:20:02下载
- 积分：1
-
arm7
ARM7 VERILOG源码，非常精简，3级流水线(ARM7 VERILOG source code, very streamlined, 3-stage pipeline)
- 2009-12-02 10:57:51下载
- 积分：1
-
In the FPGA to achieve the sound card interface, flower, filter comparators, the...
在FPGA上实现声卡接口，电子琴，滤波比较器，最终实现语音通信
-In the FPGA to achieve the sound card interface, flower, filter comparators, the eventual realization of voice communications
- 2022-01-25 20:35:57下载
- 积分：1
-
shuangerxuanyi
说明： quartusii软件仿真实验代码 双二选一(quartusii software simulation code for a pair of two elections)
- 2010-04-10 12:02:49下载
- 积分：1
-
VGA_yanse
用fpga实现VGA16色真彩的图片显示,且在AX301实验板上已经调试过(VGA16 achieve true color with fpga pictures show, and in the AX301 has been tuned breadboard)
- 2021-02-05 17:59:57下载
- 积分：1
-
本设计是针对LEON3 Altera Nios II startix2
This leon3 design is tailored to the Altera NiosII Startix2
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the test bench cannot be simulated with DDR enabled
because the Altera pads do not have the correct delay models.
* How to program the flash prom with a FPGA programming file
1. Create a hex file of the programming file with Quartus.
2. Convert it to srecord and adjust the load address:
objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec
3. Program the flash memory using grmon:
flash erase 0x800000 0xb00000
flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the
- 2022-05-18 19:00:04下载
- 积分：1
-
四通道DDS信号发生器
四通道DDS信号发生器，很好用的代码，大家一起分享(Four-channel DDS signal generator)
- 2021-03-08 14:49:28下载
- 积分：1
