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3FP
一个三分频verilog模块，可以用来学习基本结构。(A three points frequency verilog module can be used to study the basic structure.)
- 2013-08-25 00:41:29下载
- 积分：1
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verilog-montgomery-RSA
基于Montgoery 算法的RSA,FPGA verilog 实现，有测试文件(Based on Montgoery algorithm for RSA,FPGA verilog implementation，bench file)
- 2021-04-27 20:28:44下载
- 积分：1
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fir
用窗函数法设计一个线性相位FIR数字低通滤波器，用理想低通滤波器作为逼近滤波器，通带截止频率为0.2 ，阻带截止频率为0.4 ，阻带衰减不小于-40dB。(Window function method to design a linear phase FIR digital low-pass filter, as an ideal low-pass filter for approximation filter passband cutoff frequency of 0.2 stopband cutoff frequency of 0.4, the stop-band attenuation of less than-40dB.)
- 2012-09-24 13:54:07下载
- 积分：1
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add_verilog
2位全加器，实现全加器的功能，有近位的加法，输出也有近位，还有testbench,进行验证，验证通过(Two full adders, to achieve full adder function, nearly bit adder, there are nearly bit output)
- 2014-05-14 18:56:33下载
- 积分：1
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TR0114 VHDL Language Reference
TR0114 VHDL Language Reference
- 2022-03-22 11:52:47下载
- 积分：1
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sram_saa1117verilog
图像采集、存储控制verilog源代码，fpga控制SAA1117,采集数据存储到sram，仿真编译测试都能通过(Image acquisition, storage, control verilog source code, fpga control SAA1117, collecting data to sram, simulation tests can be compiled by)
- 2020-07-09 21:58:55下载
- 积分：1
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regheap
该模块实现一个寄存器堆的操作，其中前16个仅主机能写，规给为32-bit×32。后16个仅Micorblaze能写。读取没有限制。如果双方同时对同一地址进行读写操作，读回的数将是全1。(This module implement a register file of the operation, of which the first host 16 is only able to write rules to the 32-bit × 32. Micorblaze only 16 after the write. There is no limit to read. If the two sides at the same time to read and write operations to the same address, read back would have been a full one.)
- 2009-12-10 15:39:59下载
- 积分：1
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ROM的4位的话。
4 bit ROM for Quartus
- 2022-01-30 19:14:13下载
- 积分：1
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Coding Styles for if Statements and case Statements
Coding Styles for if Statements and case Statements
- 2022-02-09 23:54:06下载
- 积分：1
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VGA
verilog vga 图像处理(verilog vga)
- 2013-10-15 19:00:16下载
- 积分：1
