-
Writing-a-VHDL-Testbench
《编写VHDL测试概述》的英文原版讲述了如何使用VHDL写测试凳程序("Writing VHDL test overview" of the English original to write about how to use VHDL test bench program)
- 2014-04-03 21:57:01下载
- 积分：1
-
Quartus II TimeQuest时序分析器说明书
说明： Quartus II TimeQuest 时序分析器说明书；这本手册包含一组设计场景、约束指南以及相关建议。您应该熟悉 TimeQuest Timing Analyzer 和 Synopsys Design Constraint(SDC) 的基础知识，以便正确地使用这些指南。(Quartus II timequest timing analyzer manual; this manual contains a set of design scenarios, constraint guidelines, and related recommendations. You should be familiar with the basics of timequest timing analyzer and Synopsys design constraint (SDC) to use these guidelines correctly.)
- 2020-08-07 17:48:31下载
- 积分：1
-
实现
Implementation of
Image Processing Algorithms in FPGA Hardware.
- 2023-02-08 15:20:04下载
- 积分：1
-
Verilog_code_for_AWGN
说明： verilog实现awgn信道噪声的代码，支持可变的信噪比。利用移位寄存器来实现伪随机序列。(verilog code for implementation of awgn channel noise. support variable snr. use LSFR to implement the pseudo random sequence. )
- 2021-01-14 16:48:47下载
- 积分：1
-
AT070TN83
at070tn83 800x480 tft lcd verilog 測試 quartus 文件 (800x480 tft lcd at070tn83 testing project file)
- 2020-12-07 15:39:21下载
- 积分：1
-
mod 6 计数器
在几乎所有的数字系统，计数器被广泛使用的领域，如频率
- 2022-06-14 15:14:34下载
- 积分：1
-
med_filter
基于图像处理的中值滤波VHDL源码,能够实现对图像的滤波(Based on the median filter VHDL source image processing, image filtering can be achieved)
- 2014-07-15 10:28:28下载
- 积分：1
-
用VHDL语言实现CPLD（EPM240T100C5组成）串口接收程序
利用VHDL实现CPLD（EPM240T100C5）的串口接收程序-Using VHDL realize CPLD (EPM240T100C5) the serial receive procedure
- 2022-05-20 12:04:11下载
- 积分：1
-
zidongmen1
说明： 控制步进电机转动，正反转，旋转角度完美掌握。很好用，亲测(Control stepping motor rotation, positive and negative rotation, perfect control of rotation angle. Very easy to use, personal test)
- 2018-12-25 16:41:07下载
- 积分：1
-
8.4-ADC0809-VHDL-control-program
基于VHDL语言，实现对ADC0809简单控制(Based on VHDL language, to achieve the ADC0809 simple control)
- 2011-11-29 08:43:07下载
- 积分：1
