登录
首页 » VHDL » ac97 codec fpga vertix5

ac97 codec fpga vertix5

于 2022-02-06 发布 文件大小:5.35 kB
0 183
下载积分: 2 下载次数: 2

代码说明:

 ;建立一个录音机,用于录制和播放8位数字音频样本。实现了一个低通FIR滤波器模块,可以用作抗混叠和重构滤波器。

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • arm
    ARM教程,理解精辟,言简意赅,不错哦,欢迎大家看看(arm language )
    2009-02-18 20:06:42下载
    积分:1
  • Marquee with a program written in VHDL, and 60 binary counter program, one desig...
    一个用VHDL编写的跑马灯程序和60进制计数器的程序,一个是自己设计的一个是老师要求,都在实验箱上验证成功,希望对大家有所帮助。-Marquee with a program written in VHDL, and 60 binary counter program, one designed by one teacher asked, are in the experimental boxes proved to be successful, want to help everyone.
    2022-08-10 07:53:33下载
    积分:1
  • 123456789
    给出了SVPWM算法的详细FPGA实现方法!(A detailed FPGA SVPWM algorithm to achieve the method!)
    2017-04-05 13:50:53下载
    积分:1
  • Vivado基础实验
    通过用vivado完成一个流水灯项目手把手教你如何使用vivado,内容十分详细。(Using vivado to complete a running light project, you can learn how to use vivado by hand. The content is very detailed.)
    2018-12-06 16:14:45下载
    积分:1
  • mutiplier
    说明:  用VHDL语言仿真乘法器设计, 经过modelsim仿真, synplify综合,并下载进FPGA验证(Multiplier design using VHDL, simulation, after modelsim simulation, synplify synthesis, and downloaded into a FPGA verification)
    2009-08-28 13:28:04下载
    积分:1
  • FPGA programming serial communications, the entire source code. Including the si...
    FPGA编程实现串口通信,源代码全。包括仿真程序。-FPGA programming serial communications, the entire source code. Including the simulation program.
    2022-08-25 19:14:53下载
    积分:1
  • getCPU
    获取主机CPU信息,VS2008编译通过,含详细说明(Get information on the host CPU, VS2008 compiler, containing detailed instructions)
    2014-11-27 10:07:21下载
    积分:1
  • VHDL 100个例子
    网上分享的一段100例子,适合FPGA学习的初学者。内部还有一些经典实用技巧。                                                                        
    2022-07-27 14:30:28下载
    积分:1
  • DAC_VHDL
    DAC VHDL code using SPI method
    2016-11-09 19:53:01下载
    积分:1
  • Four-controllable-counter
    说明:  功能是(用Verilog语言的,内有比较详细的注释): (1)计数器的功能是从0到9999计数,并能以十进制数的形式在七段数码管上显示出来(包括七段数码管显示模块). (2)该计数器有一个1个nclr和一个adj_plus端,在控制信号的作用下(见下表),计数器具有复位、增或减计数、暂停的功能。编写以上的程序的完整模块. 计数器的功能表 nclr adj_minus 功 能 0 0 复位为0 0 1 递增计数 1 0 递减计数 1 1 暂停计数 (Function is (with Verilog language, the more detailed comments): (1) counter function is from 0 to 9999 counts, and are able to form a decimal number on the seven-segment LED display (including the seven-segment LED display module). (2) The counter has a one nclr and a adj_plus side, under the action of the control signal (see below), the counter has reset, increase or decrease of count pause function. Complete the preparation of the above program modules. Counter function menu nclr adj_minus reset 0 0 0 0 1 1 0 counts counting suspended Count 1 1)
    2011-03-01 22:47:51下载
    积分:1
  • 696518资源总数
  • 106242会员总数
  • 10今日下载