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IIR-digital-filter-
采用双线性变换法设计IIR数字滤波器设计的c代码,包括低通、高通和带通(Document recording the design of IIR digital filter c code)
- 2011-09-05 17:47:58下载
- 积分:1
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高清电子书-Verilog HDL数字系统设计教程4本合集
说明: 高清电子书4本合集-Verilog HDL数字系统设计教程4本合集(Digital circuit design Verilog HDL digital system design)
- 2021-02-03 16:05:58下载
- 积分:1
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LPC1788_VGA_COLOR
鼎lpc1788尚开发板的vga的显示,1024x768(lpc1788board,lcd to vga display,1024x768)
- 2014-12-15 13:34:06下载
- 积分:1
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自适应滤波器
由于衍射、散射、反射和稀疏等环境损伤的增加,其后果是信号视线的丧失和干扰。自适应信号处理可以克服这些缺陷。该代码是用甚高速硬件描述语言(VHDL)编写的,用以滤除高频,减少噪声和干扰。
- 2023-07-04 11:00:03下载
- 积分:1
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FPGA design of the guiding principles, it is classic! Want to give everyone easy
FPGA设计的指导原则,很经典的!希望给大家方便-FPGA design of the guiding principles, it is classic! Want to give everyone easy
- 2023-03-11 18:40:04下载
- 积分:1
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CORDIC_ATAN
使用verilog语言完成了基于cordic算法求反正切的计算,精度为8次迭代(Verilog language used to complete based on CORDIC algorithm for arctangent calculation, an accuracy of 8 iterations)
- 2008-12-24 11:31:00下载
- 积分:1
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High
高速多通道crc实现,可以并行实现5个通道数据的校验,支持10GB以太网标准-High-speed multi-channel crc implementation, can be achieved in parallel 5-channel data validation, support for 10GB Ethernet standard
- 2022-07-18 13:13:37下载
- 积分:1
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costas
载波同步,costas环,基于Verilog的载波同步环(Carrier synchronization, costas ring, based on Verilog carrier synchronization ring
)
- 2021-03-05 13:09:31下载
- 积分:1
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"Verilog HDL Design Guide" 4
《Verilog HDL 程序设计教程》4-"Verilog HDL Design Guide" 4
- 2023-06-21 01:20:03下载
- 积分:1
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immediate_divide_module
用组合逻辑实现循环除法器。稳定、安全、可靠。(Combinational logic loop divider. Stable, secure, and reliable.)
- 2012-08-30 09:08:04下载
- 积分:1