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Verilog HDL语言编写的5分频电路。采用两路时钟相逻辑作用产生。...
Verilog HDL语言编写的5分频电路。采用两路时钟相逻辑作用产生。-Verilog HDL prepared by the five-frequency circuits. Clock using two phase logic role.
- 2022-03-28 17:01:44下载
- 积分：1
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ORIGINAL_DOWNLOAD
说明： risc 8 by coonan compatible with PIC16C57
- 2019-12-05 20:32:55下载
- 积分：1
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ADS7870 Serial ADC Interface Using a CPLD
ADS7870 Serial ADC Interface Using a CPLD, The system
includes an XPLA3 CoolRunner CPLD, a Texas Instruments ADS7870 ADC, and a Toshiba
SRAM, All related VHDL source code is provided
- 2022-04-01 16:06:07下载
- 积分：1
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FPGA设计的I2C总线控制器的MASTER端的程序
FPGA设计的I2C总线控制器的MASTER端的程序-FPGA Design of I2C Bus Controller MASTER-side procedures
- 2022-03-14 08:16:35下载
- 积分：1
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Altium Partner SN-1000010 r10
Browser modularization processing, browser modularization combing, browser modularization expansion
- 2020-06-24 04:20:01下载
- 积分：1
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zhuangtai
状态机的典型饮用，可供学习模仿之用，四个状态，简单易学(State machine of the typical drinking, can be used to learn to imitate, four state, easy to learn)
- 2007-11-11 21:36:15下载
- 积分：1
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High-speed-digital-correlator
16位高速数字相关器的VERIOLOG程序，已经编译通过了，可以使用(16-bit high-speed digital correlator VERIOLOG program has been compiled by, you can use)
- 2020-10-09 11:37:34下载
- 积分：1
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脉动进位加法器
设计的结构是纹波进位加法器，但执行的操作是加法和减法，两种操作都是32位的，具体取决于控制信号。如果控制信号为“1”，则选择减法，然后选择“0”，然后选择加法
- 2022-02-02 17:58:16下载
- 积分：1
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analogue-digi-ana-converter
design and implementation of a format conversion system on the Altera NIOS board(QUARTUS) which reads an analogue input, converts it into digital data, and then does the reverse conversion back into analogue format. This will be done by taking an analogue an analogue input using SPI MCP3202 12-Bit A/D converter to generate the digital data stream and then the digital data will be used to generate an analogue output using Analog Devices 8-bit SPI AD7303 D/A converter.
- 2009-08-04 21:23:05下载
- 积分：1
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VHDL
先设计序列发生器产生序列：1011010001101010；再设计序列检测器，检测序列发生器产生序列，若检测到信号与预置待测信号相同，则输出“1”，否则输出“0”，并且将检测到的信号的显示出来。(First design sequence generator sequence: 1011010001101010 redesign sequence detector to detect sequence generator sequence, if the same signal is detected with the preset test signal output " 1" , otherwise " 0" , and the detection display signal out.)
- 2015-01-04 12:35:54下载
- 积分：1
