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JOP kernel, which is the core of the core, the Chinese can not find basic inform...
JOP的内核文件，这是核心的核心，中文资料基本找不到-JOP kernel, which is the core of the core, the Chinese can not find basic information
- 2022-07-20 02:09:37下载
- 积分：1
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基于Verilog HDL的完整数字跑表工程，在试验机台上运行验证通过了的。
用8位7段数码管分别显示微妙，秒，分。
有开始，暂停，复位功能。
学习...
基于Verilog HDL的完整数字跑表工程，在试验机台上运行验证通过了的。
用8位7段数码管分别显示微妙，秒，分。
有开始，暂停，复位功能。
学习VerilogHDL的经典例子，添加了显示功能。-Complete Verilog HDL-based digital stopwatch works in the test machine is running verify pass the platform. With 8-bit 7-segment digital tube showed the delicate, seconds, minutes. Has started, pause, reset. Learning VerilogHDL classic example of adding a display.
- 2022-12-27 19:50:04下载
- 积分：1
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1553B-BC-TEST
1553B总线BC端的编程例子，做通了对于一个RT的测试。对于其他的RT测试和程序的例子原理相同。(The BC end of the 1553B bus programming examples)
- 2020-12-06 21:29:21下载
- 积分：1
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Verilog keyboard input program for led lights display
verilog 键盘输入程序，用于led灯的显示-Verilog keyboard input program for led lights display
- 2023-01-08 14:55:03下载
- 积分：1
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Xilinx
说明： 2020 XILINX Vivado ISE IP License最全最可靠License获取方式。
LDPC,
CPRI,
Turbo,
Polar,
JESD204B/C
HDMI1.4/2.0,
MIPI CSI-2,
MIPI DSI
AXI CAN
AXI USB2.0
SD Card Host
Reed-Solomon Decoder/Encoder
10G Enthernet MAC
25G Enthernet MAC
40G Enthernet MAC
50G Enthernet MAC
100G Enthernet MAC
RS Encoder/Decoder
Display Port/ DP
Video Test Pattern Generator
RapidIO
tri mode ethernet mac(LDPC,
CPRI,
Turbo,
Polar,
JESD204B/C
HDMI1.4/2.0,
MIPI CSI-2,
MIPI DSI
AXI CAN
AXI USB2.0
SD Card Host
Reed-Solomon Decoder/Encoder
10G Enthernet MAC
25G Enthernet MAC
40G Enthernet MAC
50G Enthernet MAC
100G Enthernet MAC
RS Encoder/Decoder
Display Port/ DP
Video Test Pattern Generator
RapidIO
tri mode ethernet mac)
- 2020-03-11 15:40:45下载
- 积分：1
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ec11-test
台湾产数字编码电位器EC11的使用测试程序(Taiwan-digital encoder potentiometer EC11 of testing procedures)
- 2011-10-16 22:09:55下载
- 积分：1
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ofdm_baseband_design_basedon_fpga
基于Xilinx FPGA的OFDM通信系统基带设计一书的源代码 (this is source code from a book)
- 2013-06-13 22:13:52下载
- 积分：1
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RTL8369-design-kit-v3_5
RTL8369开发资料，包括手册，图纸，Layout说明等等(RTL8369 development information, including manuals, drawings, Layout Guide.)
- 2014-12-07 13:04:30下载
- 积分：1
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daojishi
用VHDL实现60秒倒计时的功能
倒计时为0时蜂鸣器持续响起(Continued sounded to achieve 60 seconds of the countdown function with VHDL countdown to the 0:00 buzzer)
- 2021-05-07 07:28:36下载
- 积分：1
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FPGA-a-CPLD-newest-Technology-guide
FPGA／CPLD技术是近年来计算机与电子技术领域的又一场革命。本书以Xilinx与Altera公司的FPGA／CPLD为主，详细介绍了FPGA／CPLD从芯片到MAX+plusⅡ、Quartus与ISE开发环境和Verilog／VHDL语言，并以交通灯逻辑控制、电子钟与点阵LED显示、LCD液晶显示及计算机ISA接口和PCI接口的设计等为例，由浅入深地详述了如何应用FPGA／CPLD进行电子设计。书中的大多数电路图和源程序已经过实例验证，读者可以直接应用于自己的设计。本书的特点是强调实用性和先进性，力求通俗易懂。
本书适用于计算机、电子、控制及信息等相关专业的在校大学生，对广大工程技术人员也具有实用价值。(FPGA/CPLD technology in recent years the field of computer technology and electronic another revolution. Book Xilinx and Altera' s FPGA/CPLD based, detailing the FPGA/CPLD from the chip to MAX+plus Ⅱ, Quartus and ISE development environment and Verilog/VHDL language and logic control traffic lights, electronic bell with dot matrix LED display , LCD liquid crystal display and computer ISA interface and PCI interface design, for example, progressive approach to detail how the application of FPGA/CPLD for electronic designs. Circuit and the source of most of the book have been instances of verification, the reader can be directly applied to their own design. Characteristic of this book is to emphasize the practical and advanced, best straightaway. This book applies to computers, electronics, control and information and other related professional college students, the majority of engineering and technical personnel also has practical value.)
- 2013-08-27 11:39:27下载
- 积分：1
