登录
首页 » VHDL » DAC0832 接口电路程序.功能:产生频率为762.9Hz的锯齿波DAC0832VHDL程序与仿真...

DAC0832 接口电路程序.功能:产生频率为762.9Hz的锯齿波DAC0832VHDL程序与仿真...

于 2022-03-12 发布 文件大小:3.39 kB
0 93
下载积分: 2 下载次数: 1

代码说明:

DAC0832 接口电路程序.功能:产生频率为762.9Hz的锯齿波DAC0832VHDL程序与仿真-DAC0832 procedures interface circuit. Functions: generate the sawtooth frequency of 762.9Hz and simulation procedures DAC0832VHDL

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 基于sopc ep2c5开发板的时间标记服务例程
    基于sopc ep2c5开发板的时间标记服务例程-Sopc ep2c5 development board based on the time-stamping services routines
    2022-02-26 04:39:24下载
    积分:1
  • dds_test
    说明:  直接数字式频率合成器DDS设计、Verilog。 产生的信号可以是正弦波或方波、三角波、锯齿波等,自选。 采用DDS技术,将所需生成的波形写入ROM中,按照相位累加原理合成任意波形。 此方案得到的波形稳定,精度高,产生波形频率范围大,容易产生高频。 本实验在设计的模块中,包含以下功能: (1)通过 freq 信号输入需要的频率的值; (2)通过 wave_sel 信号选择所需的波形; (3)通过 amp_adj 信号选择波形放大的倍数。(DDS design of direct digital frequency synthesizer, Verilog. The generated signal can be sinusoidal or square wave, triangular wave, sawtooth wave and so on, optional. By using DDS technology, the required waveforms are written into ROM, and arbitrary waveforms are synthesized according to the principle of phase accumulation. The waveform obtained by this scheme is stable, accurate and easy to generate high frequency waveform. This experiment includes the following functions in the designed module: (1) Input the required frequency value through freq signal; (2) Choosing the required waveform by wave_sel signal; (3) Select the multiplier of waveform amplification by amp_adj signal.)
    2019-01-19 16:07:50下载
    积分:1
  • greedy_snake
    基于Basys2开发板实现VGA输出,PS/2键盘接入的贪吃蛇游戏,键盘上下左右控制方向,小键盘+键控制速度,小键盘回车开始游戏,空格暂停游戏。(Basys2 based development board to achieve VGA output, PS/2 keyboard access Snake game, up and down the keyboard to control the direction, speed control keypad+ key keypad Enter to start the game, pause the game space.)
    2021-03-27 17:09:12下载
    积分:1
  • sdram_control
    SDRAM控制器 带仿真模型文件 仿真通过(Simulation model file simulation through SDRAM controller)
    2017-12-07 10:54:24下载
    积分:1
  • altera公司cycloneII全系列说明书,实用
    altera公司cycloneII全系列说明书,实用-altera" s cycloneII a full range of manual, practical
    2022-02-04 11:53:16下载
    积分:1
  • zixiechengxu
    用verilog编写的包含有与DSP通信,三电平svpwm实现的程序,(Written in verilog contains communicate with the DSP, three-level svpwm realize the procedures)
    2021-04-18 15:28:51下载
    积分:1
  • canbus verilog实现,原代码文件
    canbus verilog实现,原代码文件-canbus verilog implementation, the original source document
    2022-06-15 18:20:23下载
    积分:1
  • FPGA的I2S接收模块 audio_in_buff
    说明:  用于FPGA的I2S接收模块,仅供学习和参考(audio-i2s receive.use fpga.)
    2019-04-21 12:11:23下载
    积分:1
  • 用于实现两个数相加的vhdl代码,在相应的编译器中使用
    用于实现两个数相加的vhdl代码,在相应的编译器中使用-used to achieve the two summed VHDL code, the corresponding use of compiler
    2022-10-30 11:05:03下载
    积分:1
  • TR0114 VHDL Language Reference
    TR0114 VHDL Language Reference
    2022-03-22 11:52:47下载
    积分:1
  • 696516资源总数
  • 106571会员总数
  • 2今日下载