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用CPLD驱动扬声器实现音乐的播放，程序是用VERILOG写的，
用CPLD驱动扬声器实现音乐的播放，程序是用VERILOG写的，-CPLD driver speakers with music player, the program is written in VERILOG,
- 2022-03-20 12:37:01下载
- 积分：1
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50 cases of practical CPLD design, very classic CPLD design, including 50 typica...
CPLD实用设计50例，非常经典的CPLD设计，包含50个实际的典型应用，涉及直流电机PWM驱动，编码等内容，有了这50例，举一反三，就会了很多应用-50 cases of practical CPLD design, very classic CPLD design, including 50 typical practical applications, involving PWM DC motor driver, coding, etc., with these 50 cases, giving top priority will be a lot of applications
- 2022-02-25 20:47:07下载
- 积分：1
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counter-with-T_FF
This is counter with T_FF.
- 2016-03-26 16:36:05下载
- 积分：1
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步进电机控制程序，用vhdl实现。可实现电机的正反转控制
步进电机控制程序，用vhdl实现。可实现电机的正反转控制-Stepper motor control program, using vhdl implementation. Positive inversion of motor control can be realized
- 2022-03-03 18:23:56下载
- 积分：1
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arbitrary data source code generator
任意数据发生器的源代码-arbitrary data source code generator
- 2023-02-11 05:20:03下载
- 积分：1
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IPSO
i have coding for verilogHDL and VHDL. so please i want know that coding..
- 2012-04-24 01:01:07下载
- 积分：1
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chengxu
设计制作一个可容纳4组参赛者的数字智力抢答器，每组设置一个抢答按键；
电路具有一第一抢答信号的鉴别和锁存的功能。在主持人将系统复位并发出抢答指令后，若参加者按抢答键，则该组指示灯亮并用组别显示抢答者的组别。此时，电路具有自锁功能，使别组的抢答开关不起作用。
设置计分电路。每组在开始时预置成6分，抢答后主持人计分，答对一次加1分。(The design can accommodate a the Entrants digital intellectual Responder, each set answer in a key circuit has a first answer in the signal to identify and latch functions. Host to the system reset and sent the answer in instruction, participants answer in key, the group of the group light and display the answer in the group. At this point, the circuit has a self-locking function does not work in other groups to answer switch. Set Scoring circuit. Preset six points each at the beginning of the answer in scoring after the host, answer time, add 1 point.)
- 2012-06-10 12:58:44下载
- 积分：1
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encoder_Z64_all_rate
Wimax矩阵的LDPC编码器，已通过modelsim仿真测试，并前在altera的FPGA板上通过测试,码率5/6，可进入代码内部修改参数，支持2/3,3/4其他2个码率，数据吞吐量为700M(Wimax based LDPC encoder, modelsim simulation passed, also passed on altera FPGA board, code rate 5/6, also support 2/3,3/4, throughout 700m)
- 2012-03-19 09:44:32下载
- 积分：1
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一个用于数字解调的应用程序，主要用于数字接收机的应用方面...
一个用于数字解调的应用程序，主要用于数字接收机的应用方面-A demodulator for digital applications, mainly for the application of digital receiver
- 2022-02-01 18:38:58下载
- 积分：1
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ADS7870 Serial ADC Interface Using a CPLD
ADS7870 Serial ADC Interface Using a CPLD, The system
includes an XPLA3 CoolRunner CPLD, a Texas Instruments ADS7870 ADC, and a Toshiba
SRAM, All related VHDL source code is provided
- 2022-04-01 16:06:07下载
- 积分：1
