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用verilog编写的乒乓球游戏，内带ps2，VGA驱动，下载到spantan3开发板上即可使用（原创）...
用verilog编写的乒乓球游戏，内带ps2，VGA驱动，下载到spantan3开发板上即可使用（原创）-Prepared using Verilog table tennis game, with band ps2, VGA driver, download to spantan3 development board to use (original)
- 2023-07-23 17:15:04下载
- 积分：1
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VGA显示彩色图像，VHDL，Quartus
vga显示彩色图像ip，alter开发板-vga display color image,vhdl,quartus
- 2022-09-20 17:40:02下载
- 积分：1
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FPGA和DSP EMIFA口接口程序。在两FPGA分布
FPGA与DSP的EMIFA口接口程序.在FPGA内分配了两块双BUFFER与DSP进行通信.-FPGA and DSP EMIFA mouth interface program. The FPGA distribution within the two-SUBJECT ER and DSP communication.
- 2023-01-25 08:30:04下载
- 积分：1
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usb 硬件实现 请大家多多指教
usb 硬件实现 请大家多多指教-usb hardware realize the exhibitions please everyone
- 2022-01-28 13:02:47下载
- 积分：1
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带load、clr等功能的寄存器
带load、clr等功能的寄存器-belt load, the function clr Register
- 2022-06-20 10:15:42下载
- 积分：1
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StopWatch
This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.
- 2013-10-04 00:53:49下载
- 积分：1
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shuzi
讲述了全数字信号发生器部分频率值测算的表格(Full digital signal generator frequency value calculation form
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- 2011-12-17 00:55:01下载
- 积分：1
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开发系统上采用的时钟信号的频率是20MHz，可分别设计计数器对其计数，包括计秒、分、小时、日、周、月以及年等。在每一级上显示输出，这样就构成了一个电子日历和时钟...
开发系统上采用的时钟信号的频率是20MHz，可分别设计计数器对其计数，包括计秒、分、小时、日、周、月以及年等。在每一级上显示输出，这样就构成了一个电子日历和时钟的模型。为了可以随意调整计数值，还应包含设定计数初值的电路-Development system using the clock signal frequency is 20MHz, the design can be counter to its count, including seconds, minutes, hours, days, weeks, months and years. At every level to show the output, thus constitutes an electronic calendar and clock models. Can also adjust the order value, should also be included in setting the initial count circuit
- 2022-08-07 06:47:58下载
- 积分：1
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7_ImageEnhance
基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像增强处理,平滑,锐化,滤波(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image enhancement, smoothing, sharpening, filtering)
- 2020-10-20 21:07:24下载
- 积分：1
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complete with verilog language development USB2.0 IP source code, including docu...
完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-complete with verilog language development USB2.0 IP source code, including documentation, Simulation documents
- 2022-08-22 09:20:17下载
- 积分：1
