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vhdl
vhdl cpu芯片逻辑设计的一部分实现 只有一小部分 大家可以看一下 寄存器 加法器之类的(vhdl cpu chip logic design part of its implementation only a little part everry look and see b=about registers adder and so on)
- 2012-09-23 16:57:41下载
- 积分：1
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VHDL的重要PPT资料,对初学者非常有益处
VHDL的重要PPT资料,对初学者非常有益处-VHDL important PPT information is very useful for beginners
- 2022-05-18 19:20:34下载
- 积分：1
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interpolator
说明： 插值滤波器,用于音频解码调制解调,滤波器系数用移位相加实现(Interpolation filter, audio decoder for modulation and demodulation, filter coefficient shift combined with the realization of)
- 2008-10-21 12:49:38下载
- 积分：1
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使用vhdl语言实现对led的控制，还有电路仿真
使用vhdl语言实现对led的控制，还有电路仿真-Using vhdl language implementation of the led control, as well as circuit simulation
- 2022-03-12 11:40:55下载
- 积分：1
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Xilinx 的DDR SDRAM控制器，用Verilog HDL描述
Xilinx 的DDR SDRAM控制器，用Verilog HDL描述-
A DDR SDRAM contraller sample descripte in Verilog HDL ,base on Xilinx FPGA
- 2022-08-12 17:31:12下载
- 积分：1
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2581
Complex of three-point Gauss-lengend the Formula pi, Including orbital maneuvering simulation, initial orbit calculation, University of numerical analysis algorithms.
- 2017-09-03 10:42:39下载
- 积分：1
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采用VHDL编写的七段数码管显示程序
采用VHDL编写的七段数码管显示程序-prepared using VHDL paragraph 107 of the procedures Digital Display
- 2022-07-28 16:14:18下载
- 积分：1
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FPGA的专业综合工具，学习此第三方工具的经典教程
FPGA的专业综合工具，学习此第三方工具的经典教程-FPGA 专 业 酆 危 撸 学魏 说 叩 木坛
- 2022-05-24 03:46:54下载
- 积分：1
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altera推出的基于它们fpga和cpld的构建嵌入式系统的新技术sopc的介绍。其集成在quartus II中...
altera推出的基于它们fpga和cpld的构建嵌入式系统的新技术sopc的介绍。其集成在quartus II中-ALTERA due to launch them and they simply cpld Construction of the new Embedded System Technology sopc briefing. Its integrated into the Quartus II
- 2022-12-14 08:55:03下载
- 积分：1
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DDS_Power
FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波，方波，三角波，斜波，以及四种波形的任意两种的叠加，以及四种波形的叠加；通过控制频率控制字C的大小，以控制输出波形频率，实现1Hz的微调；通过地址变换实现波形相位256级可调；通过DAC0832使波形幅值256级可调；通过FPGA内部RAM实现波形存储回放；并实现了每秒100HZ扫频。(FPGA on the verilog language programming. Lookup table through direct digital frequency synthesis. In part through the control of the keyboard to choose sine, square, triangle wave, sloping wave, and four arbitrary waveform two superposed and the stack of four waveform; by controlling the frequency control word on the size, in order to control the output waveform frequency, 1 Hz to achieve the fine-tuning; Address transform through waveform phase adjustable 256; DAC0832 so through waveform amplitude adjustable 256; FPGA through internal RAM to the waveform storage intervals; and achieve a 100 per second sweep 9999.)
- 2007-04-17 23:43:32下载
- 积分：1
