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直方图均衡化算法
基于FPGA的直方图均衡化算法，对灰度图像增强有较好的效果。处理图像为512x512大小。包括完整的ram模块，数据通路模块，数据处理模块。
- 2022-02-06 02:41:35下载
- 积分：1
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VHDL-SUBWAY
基于QuartusII环境下的地铁自动售票系统(Subway auto ticketing system based on QuartusII)
- 2011-04-20 09:35:24下载
- 积分：1
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code
Due to its high modularity and carry-free addition, a redundant
binary (RB) representation can be used when designing high performance
multipliers. The conventional RB multiplier requires an additional RB partial
product (RBPP) row, because an error-correcting word (ECW) is generated
by both the radix-4 Modified Booth encoding (MBE) and the RB encoding.
This incurs in an additional RBPP accumulation stage for the MBE multiplier.
In this paper, a new RB modified partial product generator (RBMPPG) is
proposed; it removes the extra ECW and hence, it saves one RBPP
accumulation stage.
- 2017-10-01 23:34:56下载
- 积分：1
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conv_encoder
TD-LTE中（3.1.7）咬尾卷积码编码器verilog代码(Tail-biting convolutional code encoder verilog code)
- 2014-04-09 11:12:43下载
- 积分：1
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DES
说明： 自己写的DES的verilog实现。输入输出实现了并转串。(DES algorithm implemented in verilog.)
- 2020-12-03 16:19:25下载
- 积分：1
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EnDat
ENDAT 协议说明，包括时序等详细的说明，(endat Encoder characteristics)
- 2021-05-12 22:30:02下载
- 积分：1
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QAM_verilog
基于FPGA的16QAM，用verilog编写，其中DDS为自己编写，含设计文件和testbench。已通过moldesim软件仿真。 (FPGA-based 16QAM, with verilog writing, including DDS for their preparation, including design files and testbench. Simulation software has been through moldesim.)
- 2021-02-22 18:29:41下载
- 积分：1
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MP3
MP3解码的ASIC全部过程，包换含c和vhdl代码，样例。(MP3 decoding ASIC whole process, shifting with c and vhdl code, sample.)
- 2021-01-02 22:48:57下载
- 积分：1
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identify_F-201109A_release_notes
identify在线调试手册,主要讲了FPGA怎样在线调试文档(identity actel edition tool set release notes)
- 2012-02-02 15:53:38下载
- 积分：1
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modified_booth_multiplier
quartus ii项目文件包，功能是改进的booth乘法器，节省时钟，已完成仿真。(This zip file contains a quartus ii project, which can fufill multiple function. It is done by using a modified booth multiplier.)
- 2018-01-11 18:35:04下载
- 积分：1
