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带控制器的数据通路实现链表读和累加
一个自定义的内存,存储了一个链表,通过数据通路访问内存,读取数据,计算链表累加和,数据通路的控制器由一个有限状态机组成,实现了多状态下控制信号的产生,计算的结果回写到内存制定单元。整个过程介绍了有限状态机的设计以及数据通路控制的基本原理
- 2022-02-18 16:49:10下载
- 积分:1
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sobel
基于FPGA的Spartan-6系列的SOBEL算法实现(Implementation of SOBEL Algorithm Based on FPGA)
- 2018-05-09 15:25:33下载
- 积分:1
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80211_Transmitter_VerilogHDL
802.11a Transmitter implementation Using Verilog
- 2021-01-20 15:28:41下载
- 积分:1
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2MW_wind_grid_inverter
针对兆瓦级风电并网逆变器主电路研制中存在的并联扩容、开关频率较低和LCL滤波器难以优化设计等问题,提出了采用交流侧串接电感再进行并联的均流方案,采用载波移相技术提高变流器的等效开关频率,提出了LCL滤波器的设计原则,并给出了上述设计的理论依据和实现方法。通过对2兆瓦风电变流器主电路的仿真验证了上述技术方案。(MW-class wind power for grid-inverter main circuit of the parallel development of existing capacity, a lower switching frequency and LCL filter design difficult to optimize the problem, a series inductor AC side in parallel are further flow program, the use of carrier phase-shifting technology to enhance the equivalent converter switching frequency, a LCL filter design principles, and gives the above-mentioned theoretical basis for the design and implementation. 2 MW of wind power converter main circuit simulation program to verify the above-mentioned technology.)
- 2009-04-28 09:16:38下载
- 积分:1
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vending-machine
用Verilog实现自动售货机功能,代码较初级。易懂,内含test文件。(Automatic vending machines function with Verilog code than the primary. Understandable, containing test files.)
- 2013-11-30 20:25:34下载
- 积分:1
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verilog编写的1024点的fft快速傅立叶变换代码
verilog编写的1024点的fft快速傅立叶变换代码
- 2023-03-30 03:00:03下载
- 积分:1
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verilog uart 115200
使用verilog编写的串口uart发送模块,发送速率为115200,输入时钟为50m,多年验证无任何错误
- 2022-02-09 17:35:29下载
- 积分:1
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VIVADO 从此开始-2017.1-265_14090262
VIVADO 从此开始,详细讲解了vivado,FPGA开发工具的使用,对于初学者学习VIVADO工具很有用。(VIVADO from now on, explained in detail the use of vivado, FPGA development tools, for beginners to learn VIVADO tools very useful.)
- 2020-07-16 11:58:49下载
- 积分:1
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rs_enc
Verilog code for RS-(255,239) encoder.
- 2021-04-06 16:19:02下载
- 积分:1
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RS_5_3_CODEC
完成RS(5,3)编码程序,运用Verilog语言。(Complete the RS (5,3) coding process, the use of Verilog language.)
- 2010-05-25 21:21:34下载
- 积分:1