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CalcJavaCRC
This programa execute calc of CRC by use a table.
- 2014-08-21 23:04:30下载
- 积分：1
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mdio
使用verilog语言进行编码 完成mdio接口访问phy8201芯片的功能(Use verilog language to encode the mdio interface to access the function of phy8201 chip)
- 2018-09-18 14:20:40下载
- 积分：1
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Cmos 全加法器使用绝热逻辑
绝热电路都是使用"可逆逻辑"的低功耗电路以节省能源。与传统的CMOS电路，在开关过程中消耗能量，不同绝热电路试图节约费用由以下两个关键的规则：
永远不会打开一个晶体管时电压源之间
- 2023-04-29 04:00:02下载
- 积分：1
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GBT-15946-2008GPIB
GBT 15946-2008 GPIB可编程仪器标准数字接口的高性能协议 概述 (GBT 15946-2008 GPIB Programmable Instruments standard digital interface for high-performance protocol Overview)
- 2012-08-30 11:49:29下载
- 积分：1
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用VHDL写的源代码程序，包涵三人表决器，七人表决器，全加器以及模24，模60的计数器，都是单文件的，由于程序小又多，所以集中在一起，供新学习VHDL语言的朋友...
用VHDL写的源代码程序，包涵三人表决器，七人表决器，全加器以及模24，模60的计数器，都是单文件的，由于程序小又多，所以集中在一起，供新学习VHDL语言的朋友们参考。-With VHDL source code written procedures, includes three of the voting machine, vote on seven people, and full adder, as well as modulus 24, modulus 60 counters, are single-file, as many small procedures, so together for the new Learning VHDL Language Reference friends.
- 2022-02-02 08:32:12下载
- 积分：1
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VHDL achieve a frequency measurement of dollars, development environment for any...
一个vhdl实现的测频计,开发环境为任何支持vhdl语言的厂商提供的开发环境
-VHDL achieve a frequency measurement of dollars, development environment for any VHDL language support for manufacturers of the development environment
- 2022-01-28 17:39:53下载
- 积分：1
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i2c
说明： 本文研究的IIC总线控制器具有如下特征
1.兼容飞利浦I2C标准，以主机模式与外围设备进行数据通信，对IIC从机模型进行读/读，读/写，写/写，写/读[18]。
2.多主操作
3.软件可编程时钟频率
4.时钟拉伸和等待状态生成
5.软件可编程确认位
6.时钟同步设计
7.仲裁中断丢失，自动转移取消
8.开始/停止/重复启动检测/确认生成
9.总线忙检测(The IIC bus controller studied in this paper has the following characteristics.
1. Compatible with Philips I2C standard, data communication between host mode and peripheral devices, read/read, read/write, write/write, write/read for IIC slave model [18].
2. Multiple Main Operations
3. Software programmable clock frequency
4. Clock stretching and waiting state generation
5. Software Programmable Confirmation Bit
6. Clock Synchronization Design
7. Loss of arbitration interruption and cancellation of automatic transfer
8. Start/Stop/Repeat Start Detection/Verification Generation
9. Bus busy detection)
- 2019-06-18 12:18:10下载
- 积分：1
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程序是用硬件描述语言（VHDL）实现：4×4键…
程序主要是用硬件描述语言（VHDL）实现：
4*4键盘扫描，简洁明了，通俗易懂，比较适合VHDL初学者-procedure was used in hardware description language (VHDL) to achieve : 4* 4 keyboard scan, concise, easily understood and more suitable for beginners VHDL
- 2022-01-31 18:02:15下载
- 积分：1
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用CPLD驱动扬声器实现音乐的播放，程序是用VERILOG写的，
用CPLD驱动扬声器实现音乐的播放，程序是用VERILOG写的，-CPLD driver speakers with music player, the program is written in VERILOG,
- 2022-03-20 12:37:01下载
- 积分：1
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11阶滤波器的verilog编程语言，可很好的实现滤波功能。
11阶滤波器的verilog编程语言，可很好的实现滤波功能。-11-order filter verilog programming language, can achieve very good filtering.
- 2023-01-07 03:40:03下载
- 积分：1
