登录
首页 » VHDL » 串uart的vhdl,verilog,lattic实现原码 里面有四个文件,分别UART 源码 (lattice version)uart 源码 (Veri...

串uart的vhdl,verilog,lattic实现原码 里面有四个文件,分别UART 源码 (lattice version)uart 源码 (Veri...

于 2022-04-12 发布 文件大小:288.18 kB
0 150
下载积分: 2 下载次数: 1

代码说明:

串uart的vhdl,verilog,lattic实现原码 里面有四个文件,分别UART 源码 (lattice version)uart 源码 (Verilog)uart 源码 (VHDL)uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice version) uart source (Verilog) uart source (VHDL) uart16550.tar

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • count4
    这是一个基于Quartus2 开发环境的4输入加法器( 4adder basic on Quartus2)
    2013-08-04 09:45:07下载
    积分:1
  • dds
    基于DDS的信号源设计(包括三角波、正弦波、方波)(Design of signal source based on DDS)
    2018-01-01 18:06:51下载
    积分:1
  • 标准电视信号的同步生成程序,利用VHDL和原理图,利用Quartus综合...
    标准电视信号的同步生成程序,利用VHDL和原理图,利用Quartus综合-Standard television signal to generate the synchronization procedures, the use of VHDL and schematic diagram, using Quartus integrated
    2022-03-13 05:08:34下载
    积分:1
  • 20190717 - Copy
    说明:  this describes building spi block on verilog hdl and programming them on an fpga device
    2020-06-21 21:40:02下载
    积分:1
  • 24_Timer
    说明:  使用Verilog编写的24位定时器,具有apb 总线接口,可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)
    2021-04-27 21:38:44下载
    积分:1
  • xiaomi
    新版 小米抢购器 -源码 已经测试,代码很有用,已经抢了好几个小米3了,希望对大家有用(The new millet to snap up- source Have test, the code is useful, has robbed several millet 3, hope useful for everyone)
    2014-01-08 18:26:40下载
    积分:1
  • S3EStarter_user-guide
    Xilinx Spartan-3E Starter Kit Board User Guide(中文用户手册)(Xilinx Spartan-3E Starter Kit Board User Guide)
    2012-04-30 10:14:18下载
    积分:1
  • UART0407
    ise平台模拟UART,并与PC机实现收发(+1)(ISE platform simulation UART and transceiver.)
    2013-04-22 15:38:36下载
    积分:1
  • LATTICE_ASYNFIFO
    LATTICE FPGA FIFO 程序例程,工程详细,全部源代码上传 (LATTICE FPGA FIFO routine, detailed engineering, all source code uploaded)
    2013-09-09 11:10:01下载
    积分:1
  • 8BIT_CPU
    一个8位的CPU设计,用verilog语言写的,希望有用(A CPU OF 8 BITS )
    2020-07-01 09:00:02下载
    积分:1
  • 696518资源总数
  • 106164会员总数
  • 18今日下载