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USART
基于USART的ARM与FPGA通信实验(Based on the ARM and FPGA communication experiment of USART
)
- 2017-04-15 16:58:30下载
- 积分：1
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DDR_SDRAM_verilog
说明： DDR（双速率）SDRAM控制器参考设计verilog代码，可以直接用的，很好的(DDR (double rate) SDRAM controller reference design Verilog code, can be directly used, very good)
- 2021-03-13 16:39:24下载
- 积分：1
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concurrent
VHDL operators basics
- 2013-09-10 14:44:51下载
- 积分：1
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82 VHDL, verilog test case, involving a variety of grammatical rules. which is...
包括VHDL、verilog在内的各种设计实例，是学习硬件描述语言的帮手。共有82个实验例子，涉及各种语法规则。-82 VHDL, verilog test case, involving a variety of grammatical rules. which is you learn the HDL language helper.
- 2023-06-06 10:15:04下载
- 积分：1
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可控制器
应用背景此代码是用于执行器和传感器，可以在网络中实现一个很好的连接与其他节点和主。关键技术VHDL代码 ；可以控制位CRC校验和填料-掩模的验收规范
- 2022-01-26 00:30:01下载
- 积分：1
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wavelet
基于DB8小波变换的verilog代码设计，支持Avalon总线(Verilog DB8 Wavelet Transform Based on code design, support Avalon bus)
- 2011-01-11 13:45:55下载
- 积分：1
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NIOS II based on the SD CARD MUSIC PLAYER source, including hardware SOPC
基于NIOS II的SD CARD MUSIC PLAYER源码，包括硬件SOPC-NIOS II based on the SD CARD MUSIC PLAYER source, including hardware SOPC
- 2023-02-13 09:35:05下载
- 积分：1
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DE2_115_Synthesizer
FPGA implementation of simple Multi-tone Electronic Keyboard using DE2-115 board with a PS/2 keyboard and speaker
- 2013-08-20 19:48:32下载
- 积分：1
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ISARCSSim_az
基于压缩感知的ISAR方位向成像以及与FFT成像对比(CS-based ISAR imaging and RD imaging)
- 2013-04-07 15:16:53下载
- 积分：1
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asynchronous-clock-boundary
一个关于跨越异步时钟边界传输数据的解决方案(The solution of transfering data across asynchronous clock boundary.)
- 2011-12-21 14:30:54下载
- 积分：1
