登录
首页 » VHDL » VGA信号的产生

VGA信号的产生

于 2022-05-05 发布 文件大小:898.00 B
0 92
下载积分: 2 下载次数: 1

代码说明:

产生VGA彩条信号(Verilog 语言)-Generate VGA signal

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 交通灯电路,南北方向和东西方向分别按绿灯、黄灯、左拐灯、黄灯、红灯的顺序两灭,数码管显示相应的灯亮的时间的倒计时。已通过编译和仿真。...
    交通灯电路,南北方向和东西方向分别按绿灯、黄灯、左拐灯、黄灯、红灯的顺序两灭,数码管显示相应的灯亮的时间的倒计时。已通过编译和仿真。-Traffic light circuit, north-south direction and east-west direction respectively green, yellow light, left light, yellow light, red light destroy the order of two, a digital LED display lights the corresponding period of the countdown. Has passed the compilation and simulation.
    2023-02-22 23:25:03下载
    积分:1
  • Three
    Three-input Majority Voter -- The entity declaration is followed by three alternative architectures which achieve the same functionality in different ways. -Three-input Majority Voter -- The entity declaration is followed by three alternative architectures which achieve the same functionality in different ways.
    2022-08-12 06:51:37下载
    积分:1
  • 通用存储器VHDL代码库,The Free IP Project VHDL Free
    通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library. -generic VHDL code for memory, The Free Project VHDL IP Free-FIFO, Quartus standard library.
    2022-05-26 21:22:15下载
    积分:1
  • this come from alter ,you can look and find it on line about USB
    this come from alter ,you can look and find it on line about USB
    2023-09-06 16:15:03下载
    积分:1
  • vhdl 基于ADC0809 A/D转换控制器的设计实验
    vhdl 基于ADC0809 A/D转换控制器的设计实验-vhdl ADC0809
    2022-02-25 21:38:23下载
    积分:1
  • FM
    说明:  使用Verilog HDL ,FM调制信号。(Using Verilog, HDL, and FM modulation signals.)
    2017-10-09 22:35:11下载
    积分:1
  • 基于nios ii 控制altera de1 开发板上iic总线实现与at24c02通信
    基于nios ii 控制altera de1 开发板上iic总线实现与at24c02通信-Based on nios ii controlled altera de1 Development Board iic bus for communication with the at24c02
    2022-03-16 00:16:13下载
    积分:1
  • 用verilog编写的网卡芯片rtl级。前仿后仿都通过了,可以在modelsim上运行察看...
    用verilog编写的网卡芯片rtl级。前仿后仿都通过了,可以在modelsim上运行察看-verilogrtl After the former imitation through imitation, it can run on the look modelsim
    2022-09-01 11:30:03下载
    积分:1
  • hand_shake
    握手程序,可以完美实现跨时钟域的数据传输(handshake and testbench,verilog HDL)
    2011-11-22 21:05:38下载
    积分:1
  • 8 位 CPU vhdl实现(含全部源代码)
    说明:  这是8位CPU的CVDL代码。CPU 的主要功能是执行指令,控制完成计算机的各项操作,包括运算操作、传送操作、输入/输出操作等。作为模型计算机设计,将重点放在寄存器级,采取较简单的组成模式,以尽量简洁的设计帮助学生掌握CPU 的基本原理。 此次设计CPU就是为了了解CPU运行的原理,从而完成从指令系统到CPU的设计,并且通过仿真对CPU设计进行正确性评定。(The main function of CPU is to execute instructions, control and complete various operations of computer, including operation, transfer operation, input / output operation, etc. As a model computer design, it focuses on register level and adopts a simpler composition mode to help students master the basic principles of CPU with a concise design as far as possible. This design of CPU is to understand the principle of CPU operation, so as to complete the design from instruction system to CPU, and evaluate the correctness of CPU design through simulation.)
    2020-12-09 15:49:20下载
    积分:1
  • 696516资源总数
  • 106571会员总数
  • 2今日下载