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对于FFT的蝶形结构
图书馆IEEE;
- 2022-11-14 05:40:03下载
- 积分:1
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V2.tar
SDIO slave, written in verilog, does not support SPI mode.
- 2021-04-05 16:59:04下载
- 积分:1
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sram_saa1117verilog
图像采集、存储控制verilog源代码,fpga控制SAA1117,采集数据存储到sram,仿真编译测试都能通过(Image acquisition, storage, control verilog source code, fpga control SAA1117, collecting data to sram, simulation tests can be compiled by)
- 2020-07-09 21:58:55下载
- 积分:1
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VHDL写的PWM发生器,仿真通过,波形基本完美,可以用于直流电机的控制...
VHDL写的PWM发生器,仿真通过,波形基本完美,可以用于直流电机的控制-PWM generator written in VHDL, simulation is passed, the basic waveform perfect, can be used for DC motor control
- 2022-09-19 14:15:03下载
- 积分:1
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Ping_pong_Sparten3e-master
说明: FPGA实现乒乓球游戏 代码及仿真 VGA实现(FPGA realizes table tennis game code and simulation VGA implementation)
- 2019-05-06 20:22:13下载
- 积分:1
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16_QAM
用verilog 语言编译16QAM调制(a great complied code of 16QAM modulation for OFDM)
- 2013-09-02 16:23:40下载
- 积分:1
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sram 读写小程序,用verilog编写的,请各位高手指教
sram 读写小程序,用verilog编写的,请各位高手指教-SRAM read and write small programs using Verilog prepared, please enlighten you master
- 2022-07-03 11:53:36下载
- 积分:1
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serial port simulated programme of lattice
lattice的串口仿真的程序- serial port simulated programme of lattice
- 2023-04-29 09:40:03下载
- 积分:1
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design a module from a trip data flow channeling Lane detected bitstream "1...
设计一个模块,从一个窜行数据流里检测出码流“11100”,这个模块包括reset,clk,datain及输出端pmatch-design a module from a trip data flow channeling Lane detected bitstream "11100", this module includes reset, clk, datain and output pmatch
- 2022-07-06 13:42:26下载
- 积分:1
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In the Altera chip 2C35F672 platform FFT procedures DSPBuilder5.0, generated Ver...
在Altera芯片2C35F672平台上的FFT程序,采用DSPBuilder5.0,生成Verilog文件。开发环境:QuartusII5.0。-In the Altera chip 2C35F672 platform FFT procedures DSPBuilder5.0, generated Verilog file. Development Environment: QuartusII5.0.
- 2022-03-16 05:08:13下载
- 积分:1