-
Send-Program
program send sms by sim900 module
- 2012-08-08 18:25:11下载
- 积分:1
-
OFDM系统中的相位跟踪模块(Phase_Tracking)的FPGA实现
OFDM系统中的相位跟踪模块(Phase_Tracking)的FPGA实现-Phase_Tracking in OFDM sysytems
- 2022-10-06 04:25:03下载
- 积分:1
-
I2C总线111
说明: 此程序为调试通过的程序,带有I2C总线功能的程序.(this procedure through the debugging process, with I2C bus function procedures.)
- 2005-11-05 13:51:27下载
- 积分:1
-
数字式移相信号发生器可以产生预置频率的正弦信号,也可产生预置相位差的两路同频正弦信号,并能显示预置频率或相位差值;...
数字式移相信号发生器可以产生预置频率的正弦信号,也可产生预置相位差的两路同频正弦信号,并能显示预置频率或相位差值;-digital phase shifting generator can produce preset frequency sinusoidal signal, Preferences may also have phase difference with the way the two-frequency sinusoidal signal, and can show that the preset frequency or phase difference value;
- 2023-07-21 04:20:04下载
- 积分:1
-
Cmos 全加法器使用绝热逻辑
绝热电路都是使用"可逆逻辑"的低功耗电路以节省能源。与传统的CMOS电路,在开关过程中消耗能量,不同绝热电路试图节约费用由以下两个关键的规则:
永远不会打开一个晶体管时电压源之间
- 2023-04-29 04:00:02下载
- 积分:1
-
Frecuencymeter
Frecuencymeter digital, clk frequency 10 MHZ, exhibition in 7 segments
- 2009-09-17 02:49:40下载
- 积分:1
-
LDPC码校验节点(checknode)进行奇偶校验方程时的vhdl编程,硬件语言实现...
LDPC码校验节点(checknode)进行奇偶校验方程时的vhdl编程,硬件语言实现-LDPC check nodes (checknode) carried out at the time of parity equation VHDL programming, hardware language
- 2022-02-26 15:07:26下载
- 积分:1
-
18_vga_test
说明: 基于Xilinx Spartan6系列的fpga的VGA实现(Based on Xilinx Spartan6 series fpga VGA implementation)
- 2019-04-01 13:47:46下载
- 积分:1
-
用VHDL硬件描述语言开发的miniUART接口IP Core,用户可以将其嵌入到自己的FPGA模块中。...
用VHDL硬件描述语言开发的miniUART接口IP Core,用户可以将其嵌入到自己的FPGA模块中。-VHDL hardware description language developed by miniUART Interface IP Core, Users can be embedded into their own FPGA module.
- 2022-10-05 02:20:03下载
- 积分:1
-
can-lite-vhdl-master
说明: CAN VHDL Code. Behavioral implementation of CAN bus interface.
- 2021-01-19 21:48:41下载
- 积分:1