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DDS_signal_genarator
这是一个利用verilog语言编写的信号发生器的例子,值得参考(this is a code about signal generator by VIERILOG LANGUAGE!)
- 2013-12-23 10:12:52下载
- 积分:1
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traffic_light
完成交通灯的所有功能,已经通过验证。希望大家多多指教。(Completion of all the features of traffic lights, have been authenticated. Hope the exhibitions.)
- 2011-11-29 20:17:58下载
- 积分:1
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add4bit
一位全加器的VHDL源码与TEST BENCH.XILINX下通过(A full adder and the VHDL source code through TEST BENCH.XILINX)
- 2009-07-20 08:18:37下载
- 积分:1
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avaloncsequencer
a sequence generator
- 2009-07-27 20:59:09下载
- 积分:1
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3.3
布尔乘法器带testbench好用的工程啊(Boolean multiplier works with testbench nice ah)
- 2011-07-26 10:53:51下载
- 积分:1
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ram_dp_sr_sw[1]
dual port ram control (dual port ram control dual port ram control dual port ram control)
- 2011-06-07 10:47:03下载
- 积分:1
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m_xulie
这是用verilogHDL写的m序列发生器,简单易用,代码非常易读(It is written verilogHDL m sequence generator, easy to use, the code is very easy to read)
- 2015-05-27 20:21:26下载
- 积分:1
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gtx_interface_ip
高速串行设计FPGA-GTX IP设置生成,可动态配置速率2.4Gbps,1.2Gbps,0.6Gbps,自适应链接(High-speed serial design FPGA-GTX IP settings generated dynamically configurable rate of 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link)
- 2016-09-22 09:48:00下载
- 积分:1
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主要介绍了FPGA设计的基本原则、基本设计思想、基本操作技巧、常用模块。...
主要介绍了FPGA设计的基本原则、基本设计思想、基本操作技巧、常用模块。-Mainly introduces the basic principles of FPGA design, basic design concepts, basic operating skills, commonly used modules.
- 2022-08-25 13:03:15下载
- 积分:1
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fpq
介绍了基于VHDL的可编程分频器在波形发生器中的应用的方法,利用这一方法,
可使波形频率在大范围内变化。()
- 2007-07-24 15:46:43下载
- 积分:1