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exp_rom
通过MATLAB产生单脉冲信号的数据,存储下来作为verilog代码实现的DDS的数据源,用于验证DA数据的ddio的调试是否有问题。(The data of monopulse signal generated by MATLAB is stored as the data source of DDS implemented by Verilog code to verify whether the ddio debugging of DA data is problematic.)
- 2020-06-23 04:40:02下载
- 积分:1
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wavelet
基于DB8小波变换的verilog代码设计,支持Avalon总线(Verilog DB8 Wavelet Transform Based on code design, support Avalon bus)
- 2011-01-11 13:45:55下载
- 积分:1
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AHBtoAPB
说明: amba总线桥:ahb to asb!verilog hdl文档加代码,非常全,soc(amba bus bridge: ahb to asb! verilog hdl code for the document plus a very full, soc)
- 2021-01-05 03:48:55下载
- 积分:1
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pinlvji
verilog 简易频率计的设置,包括整个工程(verilog simple frequency meter settings, including the entire project)
- 2013-08-18 09:53:52下载
- 积分:1
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NIOSIIREV5.0
很好的学习FPGA嵌入式的资料!适合初学者和工程师参考!(Good learning FPGA embedded information! Suitable for beginners and engineers reference!)
- 2013-08-10 17:24:50下载
- 积分:1
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AD9226
一个AD9226芯片的驱动,用FPGA写的。虽然简单,但是希望对各位有帮助(An AD9226 chip driver, FPGA written. Though simple, but I hope you will help)
- 2013-09-05 01:47:36下载
- 积分:1
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ps2_lcd
此代码能够使得键盘控制液晶,实时的进行书写,按下Backspace清屏(This code enables the keyboard to control the LCD, in real-time writing, press Backspace clear the screen)
- 2013-01-27 11:04:40下载
- 积分:1
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Cache verilog代码
应用背景原创VERILOG HDL 实现数据指令CACHE的操作,LRU替换算法,包括1路组相连和2路组相连,包含ISE工程文件,亲测可用,初学者必备关键技术采用verilog语言设计的ARM cache,包含tb文件,写回策略。LRU替换算法
- 2023-05-15 11:40:03下载
- 积分:1
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Add_sub_struc
8位加减器,八位减法器与加法器,用过一个控制端可以自由变换,采用移位加法方式,用途广泛,利用减法位补码加法的理论实现。(8 addition and subtraction, eight subtractor and adder, used a control terminal can freely change the using Shift addition, a wide range of uses, the use of subtraction complement addition theory to achieve.)
- 2012-05-14 20:36:26下载
- 积分:1
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ALU_4bit
4位ALU,有两个4位输入,4位输出实现逻辑运算和算术运算,逻辑与或非,加1,减1等等功能(4 ALU, logical and arithmetic operations)
- 2012-11-18 18:04:59下载
- 积分:1