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laplace
Laplace可以应用于图像的锐化，根据其原理，对于Laplace后的图像同样可以进行边缘检测。(Laplace can be applied to image sharpening. According to its principle, edge detection can also be performed for images after Laplace.)
- 2020-07-15 18:28:50下载
- 积分：1
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用FPGA verilog hdl实现千兆以太网MAC。
用FPGA verilog hdl实现千兆以太网MAC。-Using FPGA verilog hdl realize Gigabit Ethernet MAC.
- 2022-05-10 18:11:05下载
- 积分：1
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计数器的VHDL语言程序实现1
VHDL语言编写的计数器程序，实现1到9999计数，并动态扫描显示，带清零和暂停功能，课上作业自编程序-VHDL language of the counter program to achieve 1-9999 counts, and the dynamic scan showed, with Clear and suspension of functions, classes, on a self-compiled programs
- 2022-01-21 03:16:50下载
- 积分：1
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arbitrary data source code generator
任意数据发生器的源代码-arbitrary data source code generator
- 2023-02-11 05:20:03下载
- 积分：1
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RLS.v
用verilog实现的一个2抽头RLS自适应滤波器的代码(A realization with verilog HDL code of a two-tap RLS adaprive fliter )
- 2021-04-29 11:48:43下载
- 积分：1
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Reed-Solomon-RS-ENCODE-DECODE
支持GF(2^n)域的rs编解码，可直接修改参数实现不同方式的RS编码和解码(This program is an encoder/decoder for Reed-Solomon codes.)
- 2020-12-31 09:48:58下载
- 积分：1
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cpld 控制 8
cpld 控制 8-32M sdram 控制器 maxII epm570实现。
pdf 的说明文件-CPLD control 8-32M sdram controller maxII epm570 realize. pdf documentation
- 2022-01-26 06:46:28下载
- 积分：1
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8位十六进制频率计设计 根据频率的定义和频率测量的基本原理，测定信号的频率必须有一个脉宽为1s的输入信号脉冲计数允许信号；1s计数结束后，计数值被锁入锁存器，计...
8位十六进制频率计设计 根据频率的定义和频率测量的基本原理，测定信号的频率必须有一个脉宽为1s的输入信号脉冲计数允许信号；1s计数结束后，计数值被锁入锁存器，计数器清零，为下一测频计数周期做好准备。测频控制信号可由一个独立的发生器（FTCTRL）来产生。-8-bit hexadecimal Cymometer designed in accordance with the definition of frequency and frequency of the basic principles of measurement to determine the frequency of the signal must have a pulse width of the input signal for 1s permit pulse counting signal 1s counting after the total value was locked into the lock depositors, counters cleared for the next count cycle frequency measurement ready. Frequency control signal generator may be an independent (FTCTRL) to generate.
- 2022-06-19 17:20:21下载
- 积分：1
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Verilog ADPLL文件和testbench。V
verilog ADPLL file with testbench.v
- 2022-02-25 04:56:13下载
- 积分：1
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sobel
这是本人自己编写的可用于256*256大小的图像进行sobel边缘检测的vhd文件，可在QuartusII或MaxplisII下综合和仿真，并在FPGA上测试过。可以进行修改支持其他大小图像的sobel边缘检测，同时还可以实现其它的图像模块化处理算法，例如高斯滤波，平滑等。(this is my own preparation for the 256* 256 size of the image segmentation Edge Detection vhd document in the next QuartusII or MaxplisII integrated and simulation, and the FPGA tested. Can be adapted to support other size image segmentation edge detection, It can also achieve other modular image processing algorithms, such as Gaussian filtering, smoothing and so on.)
- 2020-07-09 21:08:55下载
- 积分：1
