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使用Xilinx3S400开发的钢板检测算法中心化算法,通过测试。(a vhdl-program use Xilinx3S400)
- 2009-04-12 22:09:45下载
- 积分:1
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1553B_enc_dec
155B航空总线中曼彻斯特编码和译码模块,亲测可以使用,而且很好用,但是对锁相环的描述不是很仔细(155B Air bus Manchester encoding and decoding modules, pro-test can be used, and it just works)
- 2020-12-04 14:49:27下载
- 积分:1
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Triscend supports the use of the Model Technology ModelSim logic simulator for V...
Triscend supports the use of the Model Technology ModelSim logic simulator for VHDL simulation of
designs implemented in the Configurable System Logic (CSL) portion of a Triscend device.
- 2023-07-10 18:40:02下载
- 积分:1
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pinlvji
频率计
测量范围1-100MHz
测量阈值0.1s
计数部分为FPGA/CPLD
语言VHDL
显示部分为51
单片机加八位数码管
语言C(Frequency meter
Measuring range 1-100 MHZ
Measure threshold is 0.1 s
Count part of FPGA/CPLD
Language VHDL
Display part of 51
MCU with eight digital tube
Language C)
- 2020-10-30 20:39:55下载
- 积分:1
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ep2c5 实现 定时器
verilog语言,quartus 2 仿真
ep2c5 实现 定时器
verilog语言,quartus 2 仿真-verilog language to achieve ep2c5 timer, quartus 2 Simulation
- 2022-09-22 03:15:03下载
- 积分:1
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自动售货机
应用背景它的所有关于自动售货机项目,在两个编码,并显示出在DE2开发板关键技术= Quartus两,和DE2开发板,最好的贩卖机的客户,甚至机器,小吃的源代码,食品
- 2022-11-04 03:45:03下载
- 积分:1
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verilog,4、5分频器,5分频器占空比3:2
verilog,4、5分频器,5分频器占空比3:2-Verilog, 4,5 dividers, five dividers ratio of 3:2
- 2022-06-12 21:27:51下载
- 积分:1
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EEPROM_RD_WR
本程序包含:EEPROM的功能模型(eeprom.v)、读/写EEPROM的verilog HDL 行为模块(eeprom_wr.v)、信号产生模块(signal.v)和顶层模块(top.v) ,这样可以有一个完整的EEPROM的控制模块和测试文件,本文件通过测试。(This procedure includes: EEPROM of the functional model (eeprom.v), read/write EEPROM acts of verilog HDL modules (eeprom_wr.v), signal generator module (signal.v) and top-level module (top.v), this can have a EEPROM complete control module and test document, this document is to pass the test.)
- 2008-12-23 15:04:20下载
- 积分:1
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vhdl N
vhdl N-0.5分频方法设计,可以输入任意数值N,即分得到N-0.5的频率。-vhdl N- 0.5-frequency method, we can input arbitrary numerical N, namely, to be N- 0.5 frequencies.
- 2022-01-31 02:10:11下载
- 积分:1
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full adder设计代码,verilog 语言描述,通过modelsim 仿真,quartus综合...
full adder设计代码,verilog 语言描述,通过modelsim 仿真,quartus综合-full adder design code, verilog language to describe, through the ModelSim simulation, quartus integrated
- 2022-06-30 03:26:15下载
- 积分:1