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Xilinx-Timing
Xilinx FPGA 时序约束资料，原厂出品，经典不需要理由(Xilinx FPGA timing constraint information, original, classic no reason)
- 2013-05-17 09:31:26下载
- 积分：1
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非常好的VHDL音乐
library ieee;
use
ieee.std_logic_1164.all;
use
ieee.std_logic_unsigned.all;
entity song is
port(clk_4MHz,clk_4Hz:in std_logic;
----预置计数器和乐谱产生器的时钟
digit:buffer std_logic_vector(6 downto 0); ----高、中、低音数码管指示
zero:out std_logic_vector(4 downto 0); ----用于数码管高位置低
- 2022-12-29 04:50:03下载
- 积分：1
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arp_2
rgmii接口通讯方式，用于FPGA以太网口开发(Rgmii interface communication mode)
- 2018-11-09 21:56:27下载
- 积分：1
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procedures in the report, with QuartusII operations, the attention to word from...
程序在报告中，要 用QuartusII运行，注意从word到运行环境中，可能有个别符号不兼容，重新在运行环境中输入那些符号就可以了-procedures in the report, with QuartusII operations, the attention to word from the operating environment, Some individual symbols are not compatible, the operating environment to re-enter those symbols on the
- 2022-03-22 23:49:36下载
- 积分：1
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A useful practical VHDL Tutorial, it is suitable for beginners to learn, introdu...
一个很有用的vhdl实用教程，很适合初学者学习，介绍了vhdl的一些基本概念，还有一些经典的实例。-A useful practical VHDL Tutorial, it is suitable for beginners to learn, introduced some basic concepts of VHDL, there are some classic examples.
- 2023-02-25 04:05:07下载
- 积分：1
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vhdl-golden-reference-guide
vhdl golden reference guide
- 2012-12-31 03:56:13下载
- 积分：1
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fftshixian
基于FPGA编写的verilog代码，在xilinx上仿真实现FFT变换(FPGA-based verilog code written in xilinx FFT transform Simulation)
- 2015-04-05 11:42:08下载
- 积分：1
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ad7606
ADC7606的驱动代码，采用verilog实现(ADC7606 driver code, using Verilog to achieve)
- 2021-03-30 09:39:10下载
- 积分：1
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Electronicorgan
利用VHDL编写的电子琴发生器，以简单的演奏电路论文(Electronic organ prepared using VHDL generator to perform a simple circuit Papers)
- 2009-03-06 08:52:10下载
- 积分：1
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CPU
用Verilog实现的 哈佛结构的简单指令集CPU程序，由ALU、地址译码器、指令译码器等部分组成(Part of a simple instruction Verilog realize the Harvard architecture CPU program set by the ALU, address decoder, an instruction decoder, etc.)
- 2016-05-22 10:07:29下载
- 积分：1
