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crc_verilog_xilinx
crc校验，非常好用，是从Xilinx的IP演化来的(crc脨 拢 脩茅 拢 卢 脟 鲁 拢 潞 脙脫脙 拢 卢 脢脟)
- 2021-03-01 11:49:34下载
- 积分：1
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8psk
在matlab中8psk的调制和解调仿真程序(the modulation and demodulation of 8psk)
- 2013-05-02 09:54:07下载
- 积分：1
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__keyBoard
vhdl编写的4X4键盘扫描程序，可以有效的消除抖动，并且提供蜂鸣器输出。(VHDL prepared 4X4 keyboard scanner, you can effectively eliminate jitter and provide buzzer output.)
- 2007-10-24 09:11:11下载
- 积分：1
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包括各种类型存储器的VHDL描述，如FIFO，双口RAM等
包括各种类型存储器的VHDL描述，如FIFO，双口RAM等
-including various types of memory VHDL description, such as FIFO, Dual Port RAM, etc.
- 2022-04-11 16:05:19下载
- 积分：1
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CPLD
控制三相步进电机及光电编码器的采集,当电机停止时,保证三相里面只有一相相通,防止停止时电流过大.(Control three-phase stepper motor and optical encoder collection, when the motor stops to ensure that only one phase of three-phase inside the heart, and to prevent too much current is stopped.)
- 2008-05-26 11:37:38下载
- 积分：1
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3.4
移位除乘法器带testbench好用的工程(Useful addition to the shift multiplier works with testbench)
- 2011-07-26 10:54:46下载
- 积分：1
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VGAzifuxianshi
用VERILOG编写的VGA字符显示，可以在电脑屏幕上显示字符,已通过测试(Prepared with the VERILOG VGA character display, can display characters on a computer screen, has been tested)
- 2011-01-01 14:50:47下载
- 积分：1
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RAM存储器： 设定16 个8 位存储单元。如果read= 1 则dataout<=mem(conv_integer(address)). 如果write
RAM存储器： 设定16 个8 位存储单元。如果read= 1 则dataout
- 2022-08-05 20:01:41下载
- 积分：1
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uart
通过串口发送，实现FPGA与stm32的dds发生器(Implementation of DDS generator)
- 2018-11-28 09:19:29下载
- 积分：1
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Interfacing_RTC_with_Spartan-3_Primer_FPGA
Interfacing RTC with spartan 3
- 2013-04-04 10:13:44下载
- 积分：1
