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Simulate
FPGA控制AD逐点采集信号，并将AD转换后的数据串行发送出去。(FPGA to control the signal sampling point by point AD, AD conversion and serial data sent.)
- 2021-04-14 21:08:55下载
- 积分：1
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nco11000
实现输入一正弦波和噪声的叠加，介绍详细欢迎下载(The input of a superposition of sine wave and noise introduced in detail)
- 2010-05-16 14:19:53下载
- 积分：1
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6. For the key to enter a password lock, assuming that reset after the seven lam...
6对于进入密码锁的按键，假设复位后七个灯显示" 0"，使用sw1、sw2 2，然后只要按下并松开sw2，七个灯上就显示" 2"，而只要按下并松开sw1，七个灯上就正确显示值" 1
- 2022-03-11 23:10:49下载
- 积分：1
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ModelSim.SE.v6.0-ROR
modelsim crack versin 6
- 2009-04-30 02:23:21下载
- 积分：1
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16QAM
16QAM调制解调程序画出时域波形、 正交分量、同相分量波形，眼图，散点图等(16QAM modulation and demodulation process to draw time-domain waveform, quadrature components, in-phase component waveforms, eye diagrams, scatter plots, etc.)
- 2013-06-04 22:10:41下载
- 积分：1
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sdcard_mass_storage_controller
A host controlled ot control sd cards
- 2021-04-29 13:58:43下载
- 积分：1
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mealy fsm 和moore fsm
mealy fsm å’Œmoore fsm-mealy Fsm and moore Fsm
- 2023-04-04 18:30:04下载
- 积分：1
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VerilogHDL_advanced_digital_design_code_Ch4
Verilog HDL 高级数字设计源码 _chapter4(Advanced Digital Design Verilog HDL source _chapter4)
- 2007-11-27 10:10:43下载
- 积分：1
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Building the CPU datapath
Building the CPU datapath
- 2022-07-24 12:10:47下载
- 积分：1
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RS_Encode_Decode
RS(255,223)编解码算法。verilogHDL代码实现，在XILINX的芯片上得到验证。不包含任何IP核，方便移植到任何FPGA芯片。(RS (255223) encoding and decoding algorithm. VerilogHDL code to achieve, in the XILINX chip to be verified. Does not contain any IP core, easy to transplant to any FPGA chip.)
- 2016-01-21 12:07:34下载
- 积分：1
