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bhas
this is a vhdl program...
- 2013-08-17 23:30:56下载
- 积分：1
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dengjingdupinlv
等精度测频原理的频率计程序与仿真。。希望大家能用的到撒(such precision frequency measurement principles of Cymometer procedures and simulation. . Hope everyone can withdraw to the)
- 2006-06-09 18:15:07下载
- 积分：1
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频率计
说明： 1、能正确显示输入信号频率；
2、测量频率范围为1Hz ~ 999999Hz；
3、测量结果以十进制数字显示；
4、能测量幅值较小的信号频率；
5、有自动刷新输出数据的功能（如5s刷新一次）；
6、有自检模块（如产生100Hz的校准方波）；(1. It can correctly display the input signal frequency;
2. The frequency range of measurement is 1Hz ~ 99999hz;
3. The measurement results are displayed in decimal;
4. It can measure signal frequency with small amplitude;
5. It has the function of automatically refreshing the output data (e.g. once in 5S);
6. Self checking module (such as generating 100Hz calibration square wave);)
- 2020-03-28 16:37:56下载
- 积分：1
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关于VHDL编程的教程,比较系统的讲解,很有用的书
关于VHDL编程的教程,比较系统的讲解,很有用的书-a book about VHDL
- 2022-01-26 14:49:07下载
- 积分：1
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VHDL 算术逻辑单元ALU_复旦
我是复旦的研究生。这是用VHDL写的ALU，仿真通过，压缩包里包括了每个源代码，而且都有相应的testbench，你直接加入你的工程当中就可以进行验证。设计时。我使用Modelsim环境来编写的。
- 2023-06-11 02:05:03下载
- 积分：1
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configurable CRC Reference Design xilinx the ip, CRC_xapp562 reference design do...
可配置CRC参考设计 xilinx的ip，参考设计文档CRC_xapp562[1].pdf，VHDL语言编写的代码，包含仿真所需文件-configurable CRC Reference Design xilinx the ip, CRC_xapp562 reference design document [1]. pdf, prepared by the VHDL code The simulation includes the necessary documents
- 2022-01-26 00:23:00下载
- 积分：1
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参数化FFT源代码，点数和位宽可变，内附testbench和说明文档
参数化FFT源代码，点数和位宽可变，内附testbench和说明文档-parameters of the source code FFT, counting and variable bit-enclosing testbench and documentation
- 2022-02-20 03:06:01下载
- 积分：1
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In communication systems channel poses an important role. channels can convolve...
In communication systems channel poses an important role. channels can convolve many different kind of distortions to our information. In perticular wireless channels multipath distortion is sevear.
and more sevear is such distortion is random.
To handle this, multipath affected channels require Equalizers at receaver end.
such equalizer uses different learning Algorithms for identifying channels continuously.
This project is VHDL implementation of LMS learning algorithm with pipelined architecture. so this implementation can work with higher data rates with less clock speed requirments and so with less power consumpiton
It uses Fixed point arithmatic blocks for filtering so suitable for coustom asic.
- 2022-02-24 17:03:03下载
- 积分：1
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dct idct 编码
输入的8X8图像数据块包括在范围从0到255的整数。在DCT计算的平均值减去128从输入数据中最小的输入数据块的冗余。核心可以计算输入数据的范围128到127以及–。然后，平均值128不减。在DCT的计算，数据可以减少到重要的信息集中到少数的DCT结果，留下剩余的系数等于零。这意味着图像的能量集中 请点击左侧文件开始预览 ！预览只提供20%的代码片段，完整代码需下载后查看 加载中 侵权举报
- 2022-03-15 14:09:44下载
- 积分：1
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steper motor
stepper motor module on spartan 6 and 24MHz clock fequency
- 2019-03-10 15:44:31下载
- 积分：1
