-
iq_balance
调整iq幅度不平衡的模块,可以解决载漏和边带问题。(Iq amplitude imbalance adjustment module can be resolved carrier and sideband leakage problems.)
- 2021-04-23 17:48:47下载
- 积分:1
-
由VHDL 语言实现的数控分频
利用的是QUARTUES环境已经得到验证...
由VHDL 语言实现的数控分频
利用的是QUARTUES环境已经得到验证-By the NC VHDL language is the use of sub-frequency QUARTUES environment has been tested
- 2023-01-20 00:20:04下载
- 积分:1
-
Verilog_add_div_multi_exp
使用verilog写的32位浮点数加法模块、浮点数乘法模块、浮点数除法模块、浮点数指数模块。指数模块是综合前面三个例化成泰勒级数求指数,迭代次数(可设置)决定了精度。(Use verilog write 32-bit floating-point addition module, floating-point multiplication module, floating-point division module, the floating point number index module.Index module is a comprehensive index of the front three cases into Taylor series for calculating index, the number of iterations can be set to determine the precision)
- 2020-12-18 09:49:10下载
- 积分:1
-
一个4×4矩阵键盘接口程序的Verilog设计(FPGA)
一个4*4矩阵键盘的VERILOG接口程序设计(FPGA)-A 4* 4 matrix keyboard interface program Verilog Design (FPGA)
- 2022-07-24 14:37:13下载
- 积分:1
-
msk_mod_demod
该程序实现最小频移键控信号的调制解调,经测试无误。(The program implements minimum shift keying signal modulation and demodulation, tested and correct.)
- 2013-10-14 23:02:39下载
- 积分:1
-
四分频的程序,输出clkout0就是二分频,clkout1是四分频
四分频的程序,输出clkout0就是二分频,clkout1是四分频-Quarter-frequency process, the output clkout0 is two-way, clkout1-fourth the frequency
- 2022-02-15 17:30:06下载
- 积分:1
-
Kluwer.Academic.The.Verilog.Hardware.Description
Kluwer academic the verilog hardware description language fith edition
- 2014-10-08 08:11:42下载
- 积分:1
-
coreahblite代码
amba ahblite总线时序转并口时序,可访问sram/flash/mram,适用于smartfusion2系统,arm内核对外进行数据访问。
- 2023-08-27 04:00:03下载
- 积分:1
-
DE2_NIOSII_uCOSII_2012
一个简单的UCOSII操作系统,在DE2上面调试通过(A simple UCOSII operating systems, debugging through the DE2 above)
- 2012-08-20 10:48:08下载
- 积分:1
-
UART
说明: 使用FPGA的FIFO,状态机,乒乓操作等实现了异步UART。(The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART.)
- 2008-10-09 15:59:20下载
- 积分:1