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verilog编写的32位浮点加法器
verilog编写的32位浮点加法器-32-bit Floating Point Addition Written in Verilog
- 2022-02-21 08:09:50下载
- 积分：1
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高清电子书-Verilog HDL数字系统设计教程4本合集
说明： 高清电子书4本合集-Verilog HDL数字系统设计教程4本合集(Digital circuit design Verilog HDL digital system design)
- 2021-02-03 16:05:58下载
- 积分：1
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VHDL development of the baseball game, in QuartusII environment compiler, apply...
用VHDL开发的棒球游戏，可以在QuartusII环境下编译，适用于各种FPGA开发板。-VHDL development of the baseball game, in QuartusII environment compiler, apply to all FPGA development board.
- 2023-04-04 12:25:03下载
- 积分：1
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suzimiaobiao
数字秒表的实现，我还写个具体的过程要求等，(there is function of clock,it very useful)
- 2011-09-20 14:28:30下载
- 积分：1
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fifo
说明： FPGA的fifo与dsp的emif接口测试程序(EMIF interface test program for FIFO and DSP of FPGA)
- 2020-12-03 16:59:25下载
- 积分：1
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FPGAshixu
FPGA经验总结：时序是设计出来的
我们在做详细设计的时候，对于一些信号的时序肯定会做一些调整的，但是这种时序的调整最多只能波及到本一级模块，而不能影响到整个设计。(FPGA Experience: Timing is designed to do the detailed design of our time, for some signal timing will certainly make some adjustments, but adjust this timing can only spread to up to this level of the module, but not affect the whole design.)
- 2015-03-13 10:27:51下载
- 积分：1
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dw_ahb_dmac_db
It is Synopsys dmac controller databook
- 2020-10-10 10:27:34下载
- 积分：1
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degilent atlys board ucf
；
- 2022-04-10 00:32:44下载
- 积分：1
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VHDL硬件描述语言作业
VHDL硬件描述语言作业-VHDL hardware description language operations
- 2022-03-19 16:26:25下载
- 积分：1
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本文为verilog的源代码
本文为verilog的源代码-In this paper, the source code for Verilog
- 2022-01-24 19:02:52下载
- 积分：1
