-
lesson38_lcd1602_clander
基于Verilog语言编写的LCD1602显示的日历程序,类似时钟功能值得参考。(LCD1602 shows calendar program based on Verilog language, similar clock function is worth reference.)
- 2019-05-26 09:29:18下载
- 积分:1
-
Manip_NIOS_1
nios processor example 1
- 2015-05-22 00:17:43下载
- 积分:1
-
dividefrequency
如何用VHDL语言对时钟进行分频以达到计数目的(how to achive counting by VHDL Language)
- 2009-02-13 15:45:38下载
- 积分:1
-
D-FLIP-FLOP
ANALYSIS OF D-FLIPFLOPS
- 2013-11-12 13:35:50下载
- 积分:1
-
Yoshis_Island_(V1.0)_(U)
Bringing SMW2:YI Back To LIFE Through Rom!
- 2013-01-19 23:40:42下载
- 积分:1
-
uart
fpga串口收发完整程序,Verilog语言。(FPGA configuration PLL complete program, Verilog language.)
- 2020-06-20 17:00:02下载
- 积分:1
-
PipelineCPU
Quartus II 7.2环境中,采用硬件描述语言VHDL独立完成了基于MIPS指令集的32位RISC处理器的逻辑设计(quartusII mips pipeline 32bit cpu design)
- 2010-05-26 16:51:42下载
- 积分:1
-
BCD-counter
一个2位的BCD码十进制加法计数器电路,输入为时钟信号CLK,进位
输入信号CIN,每个BCD码十进制加法计数器的输出信号为D、C、B、A和进位输出信号COUT,输入时钟信号CLK用固定时钟,进位输入信号CIN.
(A 2-bit BCD code decimal adder counter circuit input as the clock signal CLK, a carry input signal CIN, D, C, B, A, and the carry output signal COUT, each BCD code decimal adder counter' s output signal, the input clock signal CLK Fixed clock, binary input signal CIN.)
- 2020-10-28 19:29:58下载
- 积分:1
-
一个很好的VHDL实现的功能模块程序,希望你可以用的上!
一个很好的VHDL实现的功能模块程序,希望你可以用的上!-a good VHDL functional module procedures in the hope that you can use!
- 2022-06-01 18:48:57下载
- 积分:1
-
这是一个也介绍GPIB编程的文章以及介绍GPIB协议规范
这是一个也介绍GPIB编程的文章以及介绍GPIB协议规范-This is a GPIB programming also introduced the article and introduce GPIB norm
- 2022-06-29 19:43:11下载
- 积分:1