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VHDL-the-count
利用VHDL 硬件描述语言设计一个0~9999 的加法计数器。根据一定频率的触发
时钟，计数器进行加计数，并利用数码管进行显示，当计数到9999 时，从0 开始重新计数(Use of VHDL hardware description language design a 0 ~ 9999 addition counter. According to a certain frequency of the trigger
The clock, counter add count, and use digital pipes to show that when the count to 9999, starting from 0 to count
)
- 2012-01-13 14:01:38下载
- 积分：1
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task_function
自己编写的一个verilog HDL小程序，实现基本的task调用function的功能，对初学者有用。在xilinx的ISE仿真调试通过(I have written a verilog HDL small procedures, to achieve the basic function of the task to call the function, useful for beginners. In Xilinx s ISE simulation debugging through)
- 2008-06-26 21:21:23下载
- 积分：1
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altera DE1 SD_CARD带写入一个扇区功能的程序，已确认成功，下载直接运行就可以看效果...
altera DE1 SD_CARD带写入一个扇区功能的程序，已确认成功，下载直接运行就可以看效果-altera DE1 SD_CARD with a sector write function procedures, has confirmed the success of running can be downloaded directly watch the effect of
- 2022-04-16 19:05:08下载
- 积分：1
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juanji
FPGA的卷积编码小程序，VHDL描述，参数为2，1，7.(2,1,7 cov with VHDL.)
- 2010-09-24 20:28:22下载
- 积分：1
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FPGA realization of DDS with the schematic diagram, structural clarity, the use...
用FPGA实现DDS的原理图，结构清晰，采用总线方式与外部单片机通信-FPGA realization of DDS with the schematic diagram, structural clarity, the use of bus-way communication with the outside Singlechip
- 2022-04-16 10:26:17下载
- 积分：1
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SD_Controller_Verilog
说明： 该程序包是SD卡/MMC卡控制器SDC的verilog语言包，它包括以下4部分：RTL源代码，测试平台，软件仿真文件，说明文件。(This source package is the SD card and MMC card controler model based on the Verilog language. It has the following 4 parts: RTL language, testbench, software simulating files and help document.)
- 2021-04-05 17:39:03下载
- 积分：1
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DDS FPGA开发下的verilog源代码
DDS_AD9854_for FPGA ,FPGA开发下的verilog源代码，信号发生器(DDS_AD9854_for FPGA, verilog source code, signal generator.)
- 2013-01-14 00:13:36下载
- 积分：1
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data_swith
verilog 代码实现串并转换，有延迟(Verilog code and string conversion, delay)
- 2011-07-31 23:58:17下载
- 积分：1
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多倍（次）分频器
请注意:
本例的各个源描述的编译顺序应该是:
52_divider.vhd
52_divider_...
多倍（次）分频器
请注意:
本例的各个源描述的编译顺序应该是:
52_divider.vhd
52_divider_stim.vhd-Times (times) divider Please note: This case is described in various sources to compile the order should be: 52_divider.vhd 52_divider_stim.vhd
- 2023-05-29 11:35:04下载
- 积分：1
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wbm
用walsh算法实现的符号数乘法器,asic流片时,可以不用公司的付费乘法器的ip core.(algorithm using the symbols multiplier, HDL-piece quantities. it is not necessary for the company's paid Multiplier ip core.)
- 2006-07-12 14:49:35下载
- 积分：1
