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verilog编写的流水线模块
verilog编写的流水线模块-Verilog modules prepared by the Pipeline
- 2022-03-30 09:04:46下载
- 积分:1
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ps2
PS2键盘硬件模块控制器,主要实现硬件PS2键盘的控制,适合初学verilog学者实验。(PS2 keyboard controller hardware module, the main hardware PS2 keyboard control, suitable for beginners verilog scholar experiments.)
- 2014-09-16 19:06:23下载
- 积分:1
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单片机的4 am2901完整的VHDL程序,am2901
4位MCU AM2901的完整VHDL程序,AM2901为主程序,其他为实体库-4 MCU AM2901 complete VHDL program, AM2901-based procedures, other entities, the Treasury
- 2022-12-05 05:15:03下载
- 积分:1
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8051 verilog achieve, enclosing testbench, c language debugging procedures
8051的verilog实现,内附testbench,c语言调试程序-8051 verilog achieve, enclosing testbench, c language debugging procedures
- 2022-10-21 05:35:03下载
- 积分:1
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xlj
说明: ilx554b型号CCD积分时间程序的设计,包括两座控制信号(program for ilx554b,the driver include two parts single)
- 2010-04-13 00:57:00下载
- 积分:1
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asynchronous-fifo
同步fifo的调用程序,调用Quartus II 9.0 (32-Bit)中的fifo模块(Synchronous fifo calling program, call Quartus II 9.0 (32-Bit) in fifo module)
- 2013-08-23 21:58:56下载
- 积分:1
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vhdl 基于ADC0809 A/D转换控制器的设计实验
vhdl 基于ADC0809 A/D转换控制器的设计实验-vhdl ADC0809
- 2022-02-25 21:38:23下载
- 积分:1
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EEPROM
控制器灯具有线和无线控制器采用STC11F02做的(Controller for lamp wired and wireless controller using STC11F02 to do)
- 2012-01-05 14:45:10下载
- 积分:1
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ISE7.1i 中文教程 适合xilinx的FPGA/CPLD用户
ISE7.1i 中文教程 适合xilinx的FPGA/CPLD用户-Chinese ISE7.1i the xilinx tutorial for FPGA/CPLD users
- 2022-02-25 00:06:16下载
- 积分:1
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这时一个数字钟的VHDL程序,有计时、校时、整点报时功能,很适合做EDA设计之用...
这时一个数字钟的VHDL程序,有计时、校时、整点报时功能,很适合做EDA设计之用-When a digital clock in VHDL procedures, time, school hours, the whole point timekeeping function, it is suitable for use in EDA Design
- 2022-05-22 23:36:04下载
- 积分:1