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cpld下在线资料ByteBlaster
cpld下在线资料ByteBlaster-CPLD under the online information ByteBlaster
- 2022-04-14 21:44:13下载
- 积分：1
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verilog，4、5分频器，5分频器占空比3：2
verilog，4、5分频器，5分频器占空比3：2-Verilog, 4,5 dividers, five dividers ratio of 3:2
- 2022-06-12 21:27:51下载
- 积分：1
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Calculation of square roots via ASM
算法状态机方法是一种设计有限状态机的方法。它用来表示数字集成电路的图表。ASM图类似于状态图，但形式化程度较低，因此更易于理解。ASM图表是描述数字系统顺序操作的一种方法系统。这个这项工作的目的是通过一个用vhdl编写的算法状态机（ASM）来计算一个数的平方根的整数部分。这项工作附在用葡萄牙语编写的报告之后。
- 2022-01-23 11:17:55下载
- 积分：1
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RS2
该源代码是RS（31，19）码的完整编译码程序，采用的是VerilogHDL语言，包含了RS码的编码和译码，这蛋疼的东西花费好多时间(The source code is RS (31,19) code complete encoding and decoding procedures, and spend a lot of time using is VerilogHDL language contains the encoding and decoding of RS codes, this egg pain)
- 2012-09-09 13:04:41下载
- 积分：1
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详细介绍了VHDL的28个程序。从简单到复杂。介绍详细
详细介绍了VHDL的28个程序。从简单到复杂。介绍详细-Details of the 28 procedures VHDL. From simple to complex. Detailed introduction
- 2022-07-24 10:14:53下载
- 积分：1
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A_PUF_Design
基于fpga的物理不可克隆函数（PUF）模块的实现(A PUF Design for Secure FPGA-Based Embedded Systems)
- 2014-06-28 15:37:44下载
- 积分：1
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改进的DCT算法设计，veriloghdl实现
改进的DCT算法设计，veriloghdl实现-Improved DCT algorithm design, veriloghdl realize
- 2022-03-07 20:38:18下载
- 积分：1
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ioRWTest
C6000系列之6701开发板相关文件及说明(C6000 Series of 6701 development board-related documents and notes)
- 2008-04-17 17:08:58下载
- 积分：1
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数字频率计毕业论文 不是自己做的
数字频率计毕业论文 不是自己做的-Digital Cymometer thesis do not own. . Ha ha
- 2023-05-02 09:30:02下载
- 积分：1
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通用：我新的FFT VHDL VHDL，我试图用Xilinx的FFT核，但当…
FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results.
here is what I do:
1- from core generator I choose fft core and create .vhd & .vho & .xco files.
2- I add the .xco & .vhd files to my project.
3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity of the wrapper file.-FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results.
here is what I do:
1- from core generator I choose fft core and create .vhd & .vho & .xco files.
2- I add the .xco & .vhd files to my project.
3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity o
- 2022-06-20 20:06:05下载
- 积分：1
