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Verilog keyboard input program for led lights display
verilog 键盘输入程序，用于led灯的显示-Verilog keyboard input program for led lights display
- 2023-01-08 14:55:03下载
- 积分：1
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power_control
四轴动力模块，用一个顶模块控制，输入有：油门（20档）；指令；水平仪控制指令，4个输出口(Axis power modules, with a top module control inputs are: accelerator (20 files) instruction Level control instructions, four output ports)
- 2013-12-26 20:57:03下载
- 积分：1
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hdb3_codedecode
说明： 用VERILOG实现的，hdb3编码器和解码器，经过前仿真和后仿真成功(Achieved with the VERILOG, hdb3 encoder and decoder, after a successful pre-simulation and post simulation)
- 2021-04-22 15:58:49下载
- 积分：1
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四位动态数码管显示数字时钟的分位和秒位。工具：Quartus ii 6.0 语言：VHDL...
四位动态数码管显示数字时钟的分位和秒位。工具：Quartus ii 6.0 语言：VHDL-4 shows the number of dynamic digital tube digital clock and seconds bit. Tools: Quartus ii 6.0 Language: VHDL
- 2023-08-13 03:20:02下载
- 积分：1
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FPGAPDSCDMA
上海交大关于基于FPGA的DSCDMA的实现的毕业设计(Shanghai Jiaotong University based the FPGA DSCDMA, achieve graduation design)
- 2013-02-10 14:31:46下载
- 积分：1
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a2
说明： 用MATLAB设计及FPGA实现IIR滤波器的方法
摘要 本文介绍了IIR数字滤波器的传统设计思想与步骤及计算机辅助设计方法。并在FPGA上高效实现的低阶IIR滤波
器，其阶数低，实时响应快，适合雷达等的实时、高效处理环境。利用IIR滤波器的多相结构来实现该滤波器系统的方法，对于
四通道的情形在MATLAB上利用Simulink作了仿真, 并在目标板上对算法进行了实现,证明该系统能够同时处理四个通道的信号。(Using MATLAB Design and FPGA realization IIR Filter method Abstract This paper introduces IIR digital filter traditional design Thought and steps and CAD method. And FPGA on efficient realization low IIR filter, its order low, real response fast suitable radar real time, efficient processing environment. Use IIR filter multiphase structure realize the filter systematic method, for four channel circumstances in MATLAB on use Simulink made simulation and target board algorithm was realized proved system can simultaneously four channel signal.)
- 2010-04-01 17:10:21下载
- 积分：1
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verilog编写的计算百分比模块
verilog编写的计算百分比模块-Verilog prepared by calculating the percentage module
- 2022-01-31 18:38:18下载
- 积分：1
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code for kcpcm3 : Describes the working of KCPCM3 embedded in picoblaze xilinx
code for kcpcm3 : Describes the working of KCPCM3 embedded in picoblaze xilinx-code for kcpcm3 : Describes the working of KCPCM3 embedded in picoblaze xilinx
- 2022-04-09 10:05:17下载
- 积分：1
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I2C控制核设计,由VHDL语言编写,使普通I/O端口实现I2C性能
I2C控制核设计,由VHDL语言编写,使普通I/O端口实现I2C性能-I2C control of nuclear design, VHDL language, I/O ports I2C Performance
- 2023-04-17 20:45:02下载
- 积分：1
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AXI-HP-PDMAPGIC
本文参考了Xilinx 官方文档UG873，“System Design Using Processing System High
Performance Slave Port”。主要实现了PL 中AXI CDMA IP 与PS 部分HP64bit 从接口集成。
本例中AXI CDMA 部分扮演主机，从PS 部分DDR 系统内存中源缓冲区拷贝一列数据到目
的缓冲区。可以分别采用裸机工程和基于Linux 的应用软件来实现功能。(This reference to the official document Xilinx UG873, " System Design Using Processing System High Performance Slave Port" . The main achievement of the PL in AXI CDMA IP interface integration with PS part HP64bit. In this example AXI CDMA part to play host, a copy of a column of data into the destination buffer section PS source DDR system memory buffer. Can respectively bare engineering and Linux-based applications to achieve functional.)
- 2014-12-23 10:27:24下载
- 积分：1
