登录
首页 » VHDL » VHDL由IEEE 1076标准定义的,IEEE标准的VHDL语言参考人…

VHDL由IEEE 1076标准定义的,IEEE标准的VHDL语言参考人…

于 2023-05-31 发布 文件大小:782.40 kB
0 106
下载积分: 2 下载次数: 1

代码说明:

VHDL is defined by IEEE Standard 1076, IEEE Standard VHDL Language Reference Manual (the VHDL LRM). The original standard was approved in 1987. IEEE procedures require that standards be periodically reviewed and either reaffirmed or revised. The VHDL standard was revised in 1993, 2000, and 2002. In each revision, new language features were added and some existing features enhanced. The aim in each revision was to improve the language as a tool for design and verification of digital systems. Since the 2002 revision, there have two parallel efforts to further develop the language. The first was the VHDL Procedural Interface (VHPI) Task Force, a subcommittee of the IEEE P1076 Working Group. The VHPI Task Force prepared an interim amendment to the standard, formally approved by IEEE in March 2007. The amendment is titled IEEE 1076c, Standard VHDL Language Reference Manual―Amendment 1: Procedural Language Application Interface.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 基于fpga和xinlinx ise的音乐播放器vhdl程序,希望对你有所帮助!...
    基于fpga和xinlinx ise的音乐播放器vhdl程序,希望对你有所帮助!-and xinlinx ideally music player VHDL process, and I hope to help you!
    2023-02-07 05:35:03下载
    积分:1
  • QPSK
    用Verilog语言实现QPSK调制,QPSK是一种数字调制方式。它分为绝对相移和相对相移两种。 (Verilog language using QPSK modulation, QPSK is a digital modulation. It is divided into absolute and relative phase shift of the phase shift of two.)
    2011-01-24 17:46:44下载
    积分:1
  • Xilinx_AXI
    说明:  AXI verilog designs with testbench: AXI-lite, AXI, AXI-stream
    2020-04-21 01:18:30下载
    积分:1
  • Divider
    除法器-Divider
    2022-03-22 14:47:05下载
    积分:1
  • verilog编写的1024点的fft快速傅立叶变换代码
    说明:  FFT 1024 point, in 10 state
    2020-12-18 20:29:11下载
    积分:1
  • shi01
    FPGA上机文件一所以在FPGA中采用同 步设计非常重要 MAX+PLUS II可以计算出数据传输需要(fpga Several of the largest chip operating frequency I would be grateful if the output value of counter FFFFC- FE0FF simulation waveform between the print out (only EPF10K70RC240-4 chips, the maximum allowable Clock frequency)
    2017-10-24 16:41:14下载
    积分:1
  • VHDL在SOURCEINSIGHT的插件
    VHDL在SOURCEINSIGHT的插件-VHDL in SOURCEINSIGHT plug-ins
    2022-08-13 02:07:02下载
    积分:1
  • stm32adc12路采集DMA
    adc采集多路采集多通道基于dma的adc采集(ADC acquisition, multi-channel acquisition and multi-channel acquisition)
    2020-06-19 06:20:01下载
    积分:1
  • 利用正点院子开拓者fpga实现DDS功能
    说明:  利用正点院子开拓者fpga实现DDS功能,实现三角波、正弦波、方波的发生。(Implementation of DDS with FPGA)
    2019-08-21 09:30:18下载
    积分:1
  • Circular_Buffer,流水线型多位缓存器,verilog语言描述。通过modelsim 6。0仿真,quartus 综合通过。...
    Circular_Buffer,流水线型多位缓存器,verilog语言描述。通过modelsim 6。0仿真,quartus 综合通过。-Circular_Buffer, type a number of buffer lines, verilog language description. Through modelsim 6. 0 simulation, quartus integrated through.
    2022-05-10 23:14:10下载
    积分:1
  • 696518资源总数
  • 105540会员总数
  • 37今日下载