登录
首页 » VHDL » VHDL由IEEE 1076标准定义的,IEEE标准的VHDL语言参考人…

VHDL由IEEE 1076标准定义的,IEEE标准的VHDL语言参考人…

于 2023-05-31 发布 文件大小:782.40 kB
0 118
下载积分: 2 下载次数: 1

代码说明:

VHDL is defined by IEEE Standard 1076, IEEE Standard VHDL Language Reference Manual (the VHDL LRM). The original standard was approved in 1987. IEEE procedures require that standards be periodically reviewed and either reaffirmed or revised. The VHDL standard was revised in 1993, 2000, and 2002. In each revision, new language features were added and some existing features enhanced. The aim in each revision was to improve the language as a tool for design and verification of digital systems. Since the 2002 revision, there have two parallel efforts to further develop the language. The first was the VHDL Procedural Interface (VHPI) Task Force, a subcommittee of the IEEE P1076 Working Group. The VHPI Task Force prepared an interim amendment to the standard, formally approved by IEEE in March 2007. The amendment is titled IEEE 1076c, Standard VHDL Language Reference Manual―Amendment 1: Procedural Language Application Interface.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • chuanganqi
    传感信号无线数字传输系统的设计与实现.kdh(err)
    2008-04-22 14:54:02下载
    积分:1
  • vhdl
    vhdl常见小实验代码,包括二进制比较器,4选1,8421十进制,8421转化成格雷码,8421余三码,分频器,数据码译码器,二进制减计数器,四位环形计数器等(VHDL common small experiment code)
    2020-06-24 13:00:02下载
    积分:1
  • 基于FPGA的SOPC嵌入式的流水灯的实现。
    基于FPGA的SOPC嵌入式的流水灯的实现。-Embedded FPGA-based SOPC flow light implementation.
    2022-04-11 14:07:10下载
    积分:1
  • pl_read_write_ps_ddr
    说明:  PL 和 PS 的高效交互是 zynq 7000 soc 开发的重中之重,常常需要将 PL 端的大量数据实时送到 PS 端处理,或者将 PS 端处理结果实时送到 PL 端处理,但是各种协议非常麻烦,灵活性也比较差,直接通过 AXI 总线来读写 PS 端 ddr 的数据,这里面涉及到 AXI4 协议,vivado 的 FPGA 调试等。(The efficient interaction between PL and PS is the top priority of zynq 7000 SoC development. We often need to send a large amount of data from PL to PS for real-time processing, or send the processing results from PS to pl for real-time processing. In general, we will think of using DMA for processing, but various protocols are very troublesome and the flexibility is poor. This course explains how to use Axi directly Bus to read and write DDR data of PS terminal, which involves axi4 protocol, FPGA debugging of vivado, etc.)
    2021-01-22 17:46:44下载
    积分:1
  • rs_204_188----v1.0
    RS 编码和解码Verilog Code, 实现了RS(204,188)的编码和译码;(RS Coding and Decoding Verilog code, implement RS(204,188) )
    2021-03-25 20:29:14下载
    积分:1
  • Baseband_line_code
    基于VHDL语言的基带线路码产生电路设计(毕业论文),内涵完整的源代码(Based on VHDL language baseband line code generation circuit design (Thesis), meaning the complete source code)
    2010-07-03 22:38:09下载
    积分:1
  • router_routing
    片上网络NOC基于fpga实现的,routing模块。(NOC-chip networks realized fpga-based, routing module.)
    2021-03-03 17:19:32下载
    积分:1
  • jiaotongdeng
    数字电路课程设计,用VHDL实现交通灯的控制(Digital circuit design using VHDL control of traffic lights)
    2014-06-16 18:26:53下载
    积分:1
  • simwindfarm-v1.0
    GFHGFHGFH DFHFDHD GHDHFDHHFD DFHFDHDF
    2021-04-11 22:08:57下载
    积分:1
  • FPGA realize for a good vga display routines, vhdl language.
    针对FPGA一个实现vga显示的很好的例程,vhdl语言编写。-FPGA realize for a good vga display routines, vhdl language.
    2022-01-24 09:45:51下载
    积分:1
  • 696518资源总数
  • 105895会员总数
  • 18今日下载