sparc org, vhdl rtl code

Circular_Buffer，流水线型多位缓存器，verilog语言描述。通过modelsim 6。0仿真，quartus 综合通过。-Circular_Buffer, type a number of buffer lines, verilog language description. Through modelsim 6. 0 simulation, quartus integrated through.

这是很全的标准库啊，不是1164.vhd，都是一些加，乘，除，平方等操作的包来的．-This is the standard for the whole ah, not 1164.vhd are some increases, multiplication, addition, operational square packages to come.

VHDL语言100例详解，北京理工大学ASIC研究生出版，这里是1-20个examples-VHDL language of 100 cases explain, Beijing Institute of Technology, Graduate ASIC published examples here is 1-20 months

SPI经典ip核 可以直接用于工程的开发和利用-err

Verilog，编写的udp收发程序，开发环境xilinx(Verilog, written UDP transceiver)

利用VHDL实现CPLD（EMP240T100C5）的PWM输出-Using VHDL realize CPLD (EMP240T100C5) of the PWM output

自适应均衡器

EDA/VHDL数字频率计，可编程逻辑门阵列，EDA课程设计(EDA/VHDL digital frequency meter, programmable logic gate array, EDA curriculum design)

A Full adder using half adder unit in vhdl