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数字频率计(试验报告)适合初学者参考
数字频率计(试验报告)适合初学者参考-Digtal Frequency Test(experiment report)
suit Raw recruit reference
- 2022-11-18 17:35:04下载
- 积分:1
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小波变换去噪vhdl
基于小波变换去噪,采用了vhdl编写,已经在和matlab上对比过,结果准确,而且大量的节约了时间,欢迎下载,可以在quartusii中查看RTL电路,可以在modesim中仿真出结果
- 2022-02-20 11:22:37下载
- 积分:1
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非常好的VHDL音乐
library ieee;
use
ieee.std_logic_1164.all;
use
ieee.std_logic_unsigned.all;
entity song is
port(clk_4MHz,clk_4Hz:in std_logic;
----预置计数器和乐谱产生器的时钟
digit:buffer std_logic_vector(6 downto 0); ----高、中、低音数码管指示
zero:out std_logic_vector(4 downto 0); ----用于数码管高位置低
- 2022-12-29 04:50:03下载
- 积分:1
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svpwm
空间矢量调制脉冲的产生。
感应电动机的 VHDL 代码
- 2022-07-13 19:14:01下载
- 积分:1
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This is achieved using VHDL positive and negative pulse width modulator, the sam...
这个是用VHDL实现的正负脉宽调制器,同样是对新手有帮助,高手不必看了。-This is achieved using VHDL positive and negative pulse width modulator, the same is to help novice, you do not have to read. Ha ha
- 2022-06-19 04:51:41下载
- 积分:1
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FPGAmidxilinx
基于FPGA的快速中值滤波算法,主要使用的语言是verilog 本文没有程序(FPGA-based fast median filtering algorithm, the main language used in this article does not process verilog)
- 2010-02-27 12:40:32下载
- 积分:1
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主要是RS
主要是RS-232串行接口技术并且通过了串行收发器UART的开发实例演示了接口设计的基本步骤程序-Is RS-232 serial interface technology and, through a serial UART transceiver development of interface design examples demonstrate the basic steps of the procedure
- 2022-03-17 15:36:56下载
- 积分:1
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NIOS II IDE 编程, uart_txd测试程序,仅供参考。
NIOS II IDE 编程, uart_txd测试程序,仅供参考。-NIOS II IDE programming, uart_txd testing procedures, for information purposes only.
- 2022-05-23 19:16:50下载
- 积分:1
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edc_spi_command
单片机和FPGA的通信程序,发送5个数,传输稳定,可以自行修改可一次传多个数(MCU and FPGA communication program, send five the number of stable transmission, you can modify the number may be more than one pass)
- 2013-09-14 21:09:52下载
- 积分:1
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Xilinx ISE 8.2i s license
Xilinx ISE 8.2i的license-Xilinx ISE 8.2i s license
- 2023-06-08 10:45:03下载
- 积分:1