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resolutionquartusII
用verilog编写的分辨率提高的源代码 采用双线性插值(Written resolution with the verilog source code to improve the use of bilinear interpolation)
- 2021-05-14 18:30:02下载
- 积分：1
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通用存储器VHDL代码库,The Free IP Project VHDL Free
通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library.
-generic VHDL code for memory, The Free Project VHDL IP Free-FIFO, Quartus standard library.
- 2022-05-26 21:22:15下载
- 积分：1
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VHDL language used hardware realize the serial communication of test code that c...
用硬件VHDL语言实现的串口通信的试验代码，可用来代替单片机的工作对串口进行测试。-VHDL language used hardware realize the serial communication of test code that can be used to replace the work of single-chip serial port for testing.
- 2022-06-01 13:40:50下载
- 积分：1
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用VerilogHDL编写的，一个占空比为50％的6分频电路
用VerilogHDL编写的，一个占空比为50％的6分频电路-prepared using Verilog HDL, a 50% duty cycle for the six sub-frequency circuit
- 2023-06-23 12:25:03下载
- 积分：1
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lab_5
Introduction to learn laboratry with altera quartus II 9.1
- 2016-12-12 01:24:52下载
- 积分：1
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quartus
利用拨码开关控制液晶显示器进行十进制数字显示。(DIP switches control the use of liquid crystal display to decimal figures.)
- 2020-11-24 22:49:33下载
- 积分：1
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velocity_Verilog
速度表（velocity）要求：1．显示汽车Km/h数；2．车轮每转一圈，有一传感脉冲；每个脉冲代表1m的距离；3．采样周期设为10s；
4．要求显示到小数点后边两位；5．用数码管显示；6. 最高时速小于300Km/h。（约为83.3m/s）
(use verilog to realize velocity)
- 2020-07-13 15:08:51下载
- 积分：1
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UART_FPGA
此vhdl程序实现了在FPGA上构建UART通信串口。分为两部分，UART的发送端transfer和接收端receiver。需要外部根据需求提供波特率时钟。(This program implements the building vhdl UART serial interface on the FPGA. Divided into two parts, UART transfer sender and receiver receiver. Required to provide the baud clock external demand.)
- 2015-03-04 11:02:17下载
- 积分：1
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cla - Copy
说明： ADDER USING VERILOG ADDER WITH VERILOG VERILOG ADDER
- 2019-03-19 01:35:37下载
- 积分：1
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04432909
基于FPGA实现的神经网络算法ANN。针对手势识别，不错的参考文章。(Hand Postures Recognition System Using Artificial Neural Networks
Implemented in FPGA)
- 2015-06-25 06:34:19下载
- 积分：1
