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adder8
8位加法器源代码，vivado实现编写。(8 adder Source, vivado achieve write.)
- 2015-12-01 20:35:55下载
- 积分：1
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01_test
FPGA测试程序，仅供测试硬件是否能够运行，主要功能是点亮运行指示灯(The main function of the test program of FPGA is to light the running indicator.)
- 2019-06-20 03:21:28下载
- 积分：1
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串uart的vhdl，verilog，lattic实现原码
里面有四个文件,分别UART 源码 (lattice version)uart 源码 (Veri...
串uart的vhdl，verilog，lattic实现原码
里面有四个文件,分别UART 源码 (lattice version)uart 源码 (Verilog)uart 源码 (VHDL)uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice version) uart source (Verilog) uart source (VHDL) uart16550.tar
- 2022-04-12 23:45:53下载
- 积分：1
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Detailed description of the FPGA design flow of the entire FPGA design flow full...
详细的说明了FPGA设计的整个流程
FPGA设计全流程Modelsim>>Synplify.Pro>>ISE-Detailed description of the FPGA design flow of the entire FPGA design flow full Modelsim> > Synplify.Pro> > ISE
- 2022-11-01 22:10:02下载
- 积分：1
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LCD_1602
说明： 以ISE为开发环境，Verilog语言编写程序。功能：FPGA控制 LCD_1602动态显示秒表(In the development environment of ISE, Verilog language is used to write programs. Function: LCD_1602 dynamic display stopwatch controlled by FPGA)
- 2020-06-20 00:00:02下载
- 积分：1
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JTAG design verilog code.
JTAG design verilog code.
- 2022-02-14 02:08:42下载
- 积分：1
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BCH_EncDec_Matlab
bch编解码的完整版，本人已经做过fpga实现，就是按照该程序为原型，绝对可运行(bch decoding the full version, I have done fpga implementation is in accordance with the procedure for the prototype, can certainly run)
- 2011-10-27 21:55:11下载
- 积分：1
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i2c_master_ip_for_nios
i2c master ip for altera nios, add in qsys
- 2018-03-02 14:50:44下载
- 积分：1
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cfo_correction
说明： OFDM载波同步，Verilog编写，完全正确！！！(verilog )
- 2020-11-05 21:39:50下载
- 积分：1
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数字和显示-DE2-115
这是一个设计可以执行二进制的十进制数转换的组合电路中的练习
和二进制-编码-十进制 (BCD) 加法。
- 2022-01-24 12:56:55下载
- 积分：1
