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基于FPGA的hdb3编码实现

于 2023-04-16 发布 文件大小:195.76 kB
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HDB3码是在AMI码的基础上改进的一种双极性归零码,它除具有AMI码功率谱中无直流分量,可进行差错自检等优点外,还克服了AMI码当信息中出现连“0”码时定时提取困难的缺点,而且HDB3码频谱能量主要集中在基波频率以下,占用频带较窄,是ITU-TG.703推荐的PCM基群、二次群和三次群的数字传输接口码型,因此HDB3码的编解码就显得极为重要。目前,HDB3码主要由专用集成电路及相应匹配的外围中小规模集成芯片来实现,但集成程度不高,特别是位同步提取非常复杂,不易实现。随着可编程器件的发展,这一难题得到了很好地解决。本文利用现代EDA设计方法学和VHDL语言及模块化的设计方法,设计了适合于FPGA实现的HDB3编译码器的硬件实现方案。不但克服了分立硬件电路带来的抗干扰差和不易调整等缺陷,而且具有软件开发周期短,成本低,执行速度高,实时性强,升级方便等特点。

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