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用Verlog HDL编写的数字钟程序，包含时，分，秒，进位，解码，扫描显示等功能。...
用Verlog HDL编写的数字钟程序，包含时，分，秒，进位，解码，扫描显示等功能。-Written by Verlog HDL ，a digital clock program, including hours, minutes, seconds, into the place, decoding, scanning display.
- 2023-02-05 04:55:03下载
- 积分：1
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用verilog写的CORDIC算法实现，很适合做超越函数的运算。通常用于实现正弦乘法，或者坐标变换。...
用verilog写的CORDIC算法实现，很适合做超越函数的运算。通常用于实现正弦乘法，或者坐标变换。-The cordic arithmetic implemented by verilog is adapted to exceed function.It is usually used to implement sine multiplication or coordinate tuansform.
- 2022-05-25 08:44:55下载
- 积分：1
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本程序实现不同频率时钟的产生及其相互转化
本程序实现不同频率时钟的产生及其相互转化-this program different clock frequencies to the formation and transformation
- 2022-03-06 09:31:43下载
- 积分：1
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performance with rayleigh
matlab bpsk with rayleigh performance expirement
- 2020-06-24 21:40:01下载
- 积分：1
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Basic-system-of-nexys3
the basic system of nexys3(soft core)
- 2012-09-21 23:41:14下载
- 积分：1
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divider_latest.tar
floating point divider
- 2009-11-03 11:23:16下载
- 积分：1
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arccos
一个求反余弦的cordic算法，整个工程。包括仿真。可以直接打开。(An inverse cosine of the cordic seeking algorithms, the whole project. Including the simulation. Can be directly opened.)
- 2009-11-04 22:48:00下载
- 积分：1
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pal制视频的显示
代码来源http://www.spacewire.co.uk/video.html，需要CRT显示ITU.656格式的视频的可以参考
- 2022-06-02 03:09:20下载
- 积分：1
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game
反应速度测试小游戏，最小外设cpld游戏，带设计说明书(Reaction speed test games, the minimum peripheral cpld game, with design specifications)
- 2010-05-14 18:42:57下载
- 积分：1
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src
说明： 假设每个从设备中有可访问APB寄存器16个，位宽均为32比特，16个寄存器的访问地址计算方式为 基址 + 寄存器编号左移２位（byte 偏移）(Assuming that there are 16 accessible APB registers in each slave device, the bit width is 32 bits, and the access address of 16 registers is calculated by base address + register number left shift 2 bits (byte offset).)
- 2020-12-15 13:49:14下载
- 积分：1
