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Image-Compress-FPGA_DSP
比较详细的阐述了图像压缩的原理,并基于DSP和VHDL实现该系统,最后在FPGA上通过.(More detailed exposition of the principles of image compress, and VHDL-based implementation of the system, and finally in the FPGA.)
- 2013-11-13 15:17:01下载
- 积分:1
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主要是RS
主要是RS-232串行接口技术并且通过了串行收发器UART的开发实例演示了接口设计的基本步骤程序-Is RS-232 serial interface technology and, through a serial UART transceiver development of interface design examples demonstrate the basic steps of the procedure
- 2022-03-17 15:36:56下载
- 积分:1
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apb_uart
这里是apb总线设计代码。这个源程序是基于verilog语言设计的(Here is the APB bus design code. This source program is designed based on Verilog language)
- 2021-04-12 14:18:57下载
- 积分:1
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Circular_Buffer,流水线型多位缓存器,verilog语言描述。通过modelsim 6。0仿真,quartus 综合通过。...
Circular_Buffer,流水线型多位缓存器,verilog语言描述。通过modelsim 6。0仿真,quartus 综合通过。-Circular_Buffer, type a number of buffer lines, verilog language description. Through modelsim 6. 0 simulation, quartus integrated through.
- 2022-05-10 23:14:10下载
- 积分:1
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Subway_VHDL
模拟地铁自动售票机选票、付款、取票、找零等功能,包含软件仿真和硬件响应,可供仿真测试和FPGA验证。(Analog subway ticket vending machine ballots, payment, tickets, give change and other features, including software simulation and hardware response for simulation and FPGA verification test.)
- 2016-03-14 10:44:14下载
- 积分:1
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uvm-1.2.tar
UVM 1.2 golden code, (code for UVM, )
- 2015-02-25 16:37:19下载
- 积分:1
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com1027soft
FSK/MSK/GFSK/GMSK
DIGITAL DEMODULATOR
VHDL SOURCE CODE OVERVIEW
- 2011-03-21 22:41:15下载
- 积分:1
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track_version2
说明: fpga实现相关滤波算法中的CSK算法,采用仿真的方式验证结果
fpga是xilinx
仿真工具是vivado2018.2
语言是verilog(The CSK algorithm is implemented in FPGA, and the results are verified by simulation
FPGA is Xilinx
The simulation tool is vivado 2018.2
Language is Verilog)
- 2021-04-29 16:08:42下载
- 积分:1
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1、 利用FLEX10的片内RAM资源,根据DDS原理,设计产生正弦信号的各功能模块和顶层原理图; 2、 利用实验板上的TLC7259转换器,将1中得到的正弦信...
1、 利用FLEX10的片内RAM资源,根据DDS原理,设计产生正弦信号的各功能模块和顶层原理图; 2、 利用实验板上的TLC7259转换器,将1中得到的正弦信号,通过D/A转换,通过ME5534滤波后在示波器上观察; 3、 输出波形要求: 在输入时钟频率为16KHz时,输出正弦波分辨率达到1Hz; 在输入时钟频率为4MHz时,输出正弦波分辨率达到256Hz; 4、 通过RS232C通信,实现FPGA和PC机之间串行通信,从而实现用PC机改变频率控制字,实现对输出正弦波频率的控制。-a use FLEX10-chip RAM resources, in accordance with DDS principle, design sinusoidal signal generated by the top-level functional modules and schematics; 2, the experimental board TLC7259 converters, will be a sinusoidal signal, the D/A conversion, after filtering through the ME5534 oscilloscope observation; 3, the output waveform requirements : the input clock frequency of 16KHz, sine wave output resolution of 1Hz; the input clock frequency of 4MHz, the sine wave output resolution of 256Hz; 4, RS232C communications, FPGA and PC serial communications between in order to achieve PC-frequency control characters, the realization of sine wave output frequency control.
- 2022-01-25 19:12:14下载
- 积分:1
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gtwizard_254_127_ex_1113_3
配置GTH ip的例子工程,选用7 series 芯片的GTH 113quad的四个通道,在程序中每个链路利用自己的恢复时钟进行数据解码,所以四个通道可以各自独立运行;成功工作在2.54Gb/s的链路状态,长时间(>24小时)的测试,误码率一直为0.(The GTH ip example project is configured with four channels of the GTH 113quad of the 7 series chip. Each link in the program uses its own recovery clock for data decoding, so the four channels can operate independently; the successful operation is at 2.54Gb/ The link state of s, long time (>24 hours) test, the bit error rate has been 0.)
- 2019-06-17 21:33:56下载
- 积分:1