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在 FPGA 中实现 SPI 接口
在 FPGA，SPI、 I2C 等 ASI，串行接口的实现来武力作为需要实现外围设备之间的接口。这个项目给 VHDL 源代码实施 SPI 接口和他们有关的文件。
- 2022-12-01 01:55:04下载
- 积分：1
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the CD
本CD-ROM包括《Verilog-HDL实践与应用系统设计》一书中的全部例子，这些例子全部通过了验证。第七章以后的设计实例，不仅有Verilog-HDL的例子，也附了包括VB、VC++等源程序,甚至将DLL的生成方法也详尽地作了说明。
-the CD-ROM include "Verilog-HDL Practice and Application System Design," a book the whole Examples of these examples were passed certification. After the seventh chapter, a design example is not only Verilog-HDL example, the report include VB, VC and other source files, even DLL generator also described in detail.
- 2023-04-27 17:15:04下载
- 积分：1
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一个用VHDL语言编写的双端口存储器程序，可下载在FPGA中使用
一个用VHDL语言编写的双端口存储器程序，可下载在FPGA中使用-Written in VHDL language using a dual-port memory program can be downloaded in the FPGA using
- 2023-06-18 05:20:03下载
- 积分：1
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8051IP nuclear source code (VHDL). RAR
8051IP 核源代码（VHDL）.RAR-8051IP nuclear source code (VHDL). RAR
- 2022-11-14 08:05:04下载
- 积分：1
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CODE_VHDL_COUNTING 0 到 9 (慈 0 đến 9 Đếm hiển đoạn 施耐 1 带领 7)
CODE_VHDL_COUNTING 0 到 9 (慈 0 đến 9 Đếm hiển đoạn 施耐 1 带领 7)
- 2023-04-13 10:55:04下载
- 积分：1
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nerualnetwork
本文为通信专业硕士研究生的毕业论文。主要研究神经网络的FPGA实现及其在网络拥塞控制中的应用。
(In this paper, for the communications professional Master s thesis. Major study of the FPGA realization of neural networks and its application in network congestion control applications.)
- 2008-12-14 01:37:03下载
- 积分：1
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ps2接口源程序。标准的键盘和鼠标接口，在Xilinx SpartanII XC2S200 实验板上通过验证...
ps2接口源程序。标准的键盘和鼠标接口，在Xilinx SpartanII XC2S200 实验板上通过验证-ps2 interface source. Standard keyboard and mouse interface, in the experiments on-board Xilinx SpartanII XC2S200 validated
- 2023-03-24 22:15:03下载
- 积分：1
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Verilog-detail
不错的verilog学习语言资料，详细地对verilog语言中的重要语句应用进行分析。(A good the verilog learn language information, verilog language statement application.)
- 2013-03-26 13:01:23下载
- 积分：1
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TOFED_TB_1
A 4 bit twisted ring counter is a sequential circuit which produces the following sequence of
output values: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001 and then repeats. Design a
circuit for a 4 bit twisted ring counter that uses four D flip flops. Draw a state transition
diagram, a state table and a schematic for your circuit. Design an alternate implementation
using just three flip flops and draw a state transition diagram, state table and a schematic
for your circuit. If your designs are extended to implement an n bit twisted ring counter,
how many flip flops are required using each of the two approaches. In what situations
would you prefer the first method? In what situations would you prefer the second?
- 2014-11-08 06:58:55下载
- 积分：1
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这是一个基于FPGA实现的GPS的程序，保证可以用
这是一个基于FPGA实现的GPS的程序，保证可以用-This is an FPGA-based GPS program to ensure that you can use ... ...
- 2022-05-05 21:41:30下载
- 积分：1
