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VHDL prepared by the FIR filter source for Embedded designers have a good role i...
VHDL语言编写的FIR滤波器源码
对于嵌入式设计者有很好的指导作用
-VHDL prepared by the FIR filter source for Embedded designers have a good role in guiding
- 2022-06-17 20:08:46下载
- 积分：1
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Fractional_Time_Delay
Used for Time shifting discrete signals, it can do both integral and fractional sampling period delay. Original.
- 2020-12-16 22:29:12下载
- 积分：1
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HDMI_FPGA
该源码可基于FPGA设置多分辨率的HDMI显示，且其包含了完整的时序和端口、地址映射，可以很方便的将其移植(The source code can be set based on FPGA multi-resolution HDMI display, and it includes a complete timing and port, address mapping, it can be easily transplanted)
- 2020-12-17 11:09:12下载
- 积分：1
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coe
自动计算fir滤波器系数的工具，不妨一试(Automatic calculation of filter coefficients fir tools, try)
- 2009-04-11 17:20:49下载
- 积分：1
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Hardware-CNN-master
Convolutional neural network code for fpga
- 2019-02-27 15:21:22下载
- 积分：1
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ex11
说明： 该模块实现了FPGA的uart串口收发功能(The module realizes UART serial port transceiver function of FPGA)
- 2020-09-09 11:58:09下载
- 积分：1
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1pps
说明： fpga程序，产生1pps脉冲信号，使用的verilog语言。(FPGA program generates 1 PPS pulse signal, using Verilog language.)
- 2020-06-20 17:00:01下载
- 积分：1
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Single-CPU
简单的单周期CPU设计，实现的指令有：算术运算指令、逻辑运算指令、移位指令、比较指令、存储器读/写指令、分支指令、跳转指令、停机指令。(Simple single-cycle CPU design,The instructions implemented are as follows:Arithmetic operation instruction, logical operation instruction, shift instruction, comparison instruction, memory read/write instruction, branch instruction, jump instruction, stop instruction.)
- 2020-06-16 12:28:32下载
- 积分：1
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signalintegrity
信号完整的一些总结，非常实用，适合开始着使用(A book for signal integrated)
- 2014-08-08 16:45:47下载
- 积分：1
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QPSK
In this case is a QPSK algorithm code for mapping the interleaved code, using VHDL language. This code provide the method of mapping the code by using QPSK algorithm.
- 2014-11-19 04:27:20下载
- 积分：1
