登录
首页 » VHDL » HDL的例子源代码3 / 5

HDL的例子源代码3 / 5

于 2022-07-26 发布 文件大小:288.64 kB
0 124
下载积分: 2 下载次数: 1

代码说明:

HDL example source code 3/5 jkff_a

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 数字相位
    PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上;顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the lock data the rising and falling edge; top-level document is PLL.GDF
    2023-05-28 08:00:03下载
    积分:1
  • ad0809
    对ad0809的控制代码( ad0809control)
    2010-08-28 15:00:50下载
    积分:1
  • booth4
    4位的booth算法加法器,对计算机组成原理的学习有帮助,verilog语言编写(4-bit adder booth algorithm, the learning of computer organization help, verilog language)
    2010-09-27 04:49:51下载
    积分:1
  • pgaasm
    is61lv25616简单的verilog程序,完成sram读写 主要是基于FPGA(EP2C8Q208I8)下的SRAM驱动(1lv25616 simple verilog program, complete sram read and w1lv25616 simple verilog program, complete sram read)
    2017-06-19 13:08:08下载
    积分:1
  • 基于FPGA的八位RISC CPU的设计
    基于FPGA的八位RISC CPU的设计-FPGA-based RISC CPU design eight ....
    2022-04-07 11:51:38下载
    积分:1
  • 2022-01-25 14:18:53下载
    积分:1
  • LCD1602
    通过编写verilog语言完成数据的在液晶LCD1602显示(By writing verilog language to complete the data displayed on the LCD LCD1602)
    2013-08-04 13:12:05下载
    积分:1
  • algorithm_design_and_logic_implemention
    本书作者为夏宇文,详细讲解了从算法设计与验证到硬件逻辑实现的过程,要求读者有一定的verilog基础(This book author XIA Yu-Wen gave a detailed account from algorithms to hardware logic design and verification of implementation process, requiring readers to have some basis for verilog)
    2009-11-11 21:19:03下载
    积分:1
  • spi
    VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.(SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the )
    2021-04-29 10:58:43下载
    积分:1
  • vga_ctl_640x480
    VGA 640x480 driver in verilog
    2010-08-16 02:48:43下载
    积分:1
  • 696518资源总数
  • 106164会员总数
  • 18今日下载