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Verilog版的C51核(OC8051)
Verilog版的C51核(OC8051)-Verilog version of the C51 core (OC8051)
- 2022-04-30 06:36:25下载
- 积分:1
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DA
说明: DOCUMENT ON DISTRIBUTED ARITHMATIC
- 2014-02-05 17:06:51下载
- 积分:1
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基于FPGA的数字钟设计
基于FPGA的数字钟的设计,外部时钟32MHz,通过分频器得到秒脉冲,用于正常工作时的计数脉冲。通过分频还得到一个5ms的脉冲,用于按键的消抖(具体原理可见程序)。输入的信号有三个:1.时钟信号2.校时模式设置按键3.校时调整按键,输出通道6位数码管。共有:校时模块,24计数的小时计数模块,60计数的分钟计数模块,60计数的秒钟计数模块。
- 2022-04-01 05:03:17下载
- 积分:1
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本文提供了一个CMOS控制器,使Nios II可以利用C.
本文提供了一种CMOS控制器,使Nios-II可以利用CMOS控制器控制CMOS,并允许在CMOS图像上传送SDRAM。在DE2-70平台上运行
- 2022-02-12 08:29:38下载
- 积分:1
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SMBus
SMBus控制器的VHDL源码程序,适用于Quartus2,ISE等开发环境。(The SMBus controller VHDL source code procedures applicable to Quartus2 ISE development environment.)
- 2021-03-24 18:39:14下载
- 积分:1
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cycloneIII_3c120_dev_power_demo
cycloneIII_3c120_dev_power_demo atlera公司官方例程(cycloneIII_3c120_dev_power_demo atlera company official routines)
- 2014-12-15 17:09:14下载
- 积分:1
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sample_tcam.tar
verilog RTL code for simple TCAM
- 2014-06-25 15:50:08下载
- 积分:1
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[verilog]dcfifo_256x32
双时钟域FIFO(This is self-defined Dual-Clock FIFO, using logic lut resources.
Dual-Clock FIFO,
Depth: 256
Width: 32
USEDW: Y
FULLL:Y
EMPTY:Y)
- 2017-05-10 13:25:41下载
- 积分:1
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8b10b_xilinx
xilinx 的8B10B编解码源码, 里面有仿真模型,用以测试验证(xilinx 8B10B encode/decode source)
- 2018-07-20 16:02:29下载
- 积分:1
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qpsk_demod_use_FPGA
根据软件无线电的思想,提出了一种新颖的数字信号处理算法,对QPSK信号的相位进行数字化处理,从而实现对QPSK信号的解调.该算法允许收发两端载波存在频差,用数字锁相实现收发端载波的同步,在频偏较大的情况下,估算频偏的大小,自适应设置环路的带宽,实现较短的捕获时间和较好的信噪性能。整个设计基于XILINX公司的ISE开发平台,并用Virtex-II系列FPGA实现。用FPGA实现调制解调器具有体积小、功耗低、集成度高、可软件升级、扰干扰能力强的特点,符合未来通信技术发展的方向。(According to the idea of software radio, a novel digital signal processing algorithm, the phase of QPSK digital signal processing, enabling the demodulation of QPSK signals. This algorithm allows the sending and receiving ends of the carrier frequency difference exists, using digital phase-locked to achieve synchronization of sending and receiving end of the carrier, in the case of large frequency offset, frequency offset estimation of the size, adaptive set the loop bandwidth to achieve shorter acquisition time and better noise performance. The whole design is based on the company XILINX ISE development platform, and Virtex-II series with the FPGA. FPGA realization of a modem with a small size, low power consumption, high integration, software upgrades available, the characteristics of strong interference interference, in line with the future direction of ICT development.)
- 2010-12-06 10:52:36下载
- 积分:1