-
FPGA_MVB
此论文想详细阐明了用FPGA做硬件处理，集成SOPC功能实现MVB通讯协议的解决方案，可以运行在alter fpga上面。(This paper expounds in detail the processing to do with FPGA hardware, integrated solutions for SOPC function of the realization of MVB communication protocol, can run in alter FPGA above.)
- 2021-01-03 17:58:56下载
- 积分：1
-
自己使用VHDL语言编写的24位寄存器.主要用于DDS中
自己使用VHDL语言编写的24位寄存器.主要用于DDS中-24bit_register
- 2022-09-06 21:25:03下载
- 积分：1
-
My-Simple-Specturm--Analyzer
基于LabVIEW FPGA的频谱估计与分析(the power spectrum estimation and analysis based on LabVIEW FPGA)
- 2013-11-13 08:45:40下载
- 积分：1
-
seven-voting
用verilog 语言实现七人投票表决器(verilog seven voting)
- 2020-09-24 10:57:48下载
- 积分：1
-
QPSK_System
实现QPSK系统的调制解调仿真，基带成形滤波器采用升余弦滚降滤波器，将仿真的误码率与理论误码率作了比较(Implement QPSK modulation and demodulation simulation system, the baseband shaping filter using Raised Cosine filter will BER simulation were compared with the theoretical BER)
- 2020-12-22 15:39:07下载
- 积分：1
-
DW_apb_rtc
verilog实现RTC功能，可直接用于芯片开发中。(verilog achieve RTC function can be directly used for chip development.)
- 2020-12-28 16:49:01下载
- 积分：1
-
键盘输入液晶模块显示字符,在液晶显示屏上显示从PS2键盘输入的字符...
键盘输入液晶模块显示字符,在液晶显示屏上显示从PS2键盘输入的字符-Keyboard input LCD display module characters displayed in the LCD screen from the PS2 keyboard input characters
- 2022-10-02 08:20:03下载
- 积分：1
-
Slave-FIFO
详细讲解Slave FIFO模式下的初始化设置和相对应寄存器说明(Explain in detail the initial setup Slave FIFO mode and the corresponding register description)
- 2014-03-18 17:33:23下载
- 积分：1
-
chenxu
电子时钟，可以显示四位，两位显示分钟，两位显示秒，可以用按键控制清零，以及加减数(Electronic clock, you can display four bit, two bit display minutes, the second display seconds, can be used to control the key to clear, and the addition of subtraction)
- 2017-04-22 21:29:14下载
- 积分：1
-
Verilog HDL语言编写的5分频电路。采用两路时钟相逻辑作用产生。...
Verilog HDL语言编写的5分频电路。采用两路时钟相逻辑作用产生。-Verilog HDL prepared by the five-frequency circuits. Clock using two phase logic role.
- 2022-03-28 17:01:44下载
- 积分：1
