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ccd_tcp1209d-driver
ccd驱动程序,刺程序是tcd1209的驱动程序，能够修改积分时间(ccd driver stabbed program is tcd1209 driver can modify the integration time)
- 2021-02-23 09:49:40下载
- 积分：1
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FPGA使用串口实现字节拼接传输更大的数据
FPGA使用串口实现字节拼接传输更大的数据，通过修改代码可以实现任意字节的拼接，并通过自己设定通信协议可以实现与STM32的通信，达到简单而又高效率的通讯效果
- 2023-03-07 05:50:03下载
- 积分：1
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xilinx-timing-constrains
ISE时序约束笔记——Global Timing Constraints，这个文档中详细介绍了如何使用ISE中约束工具和原理，对fpga水平提高有很大帮助(In this file , global timing constraints is introduced very clearly. It can really helps)
- 2012-04-16 11:08:45下载
- 积分：1
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test_vhdl
vhdl测试程序，用于初雪者熟悉hdl的具体语法应用。比较简单了。(VHDL test procedure for the First Snow hdl who are familiar with the application of specific syntax. A relatively simple.)
- 2009-01-09 18:25:34下载
- 积分：1
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unishift
An universal shift register performs the following tasks load, right shift ,left shift and parallel load as the selection inputs are 00,01,10,11 respectively. Such a register is implemented here in Quartus.
- 2009-09-24 18:56:48下载
- 积分：1
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iic
iic 总线 verilog 源代码
标准i2c总线， 有sda scl 时钟，频率自定(IIC bus standard Verilog source code i2c bus, has sda scl clock, the frequency of self-)
- 2007-10-24 17:52:33下载
- 积分：1
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FPGA读写SDRAM的实例
FPGA对SDRAM进行读写测试程序，亲测有效无误。(FPGA reads and writes test programs for SDRAM.)
- 2017-09-18 14:51:53下载
- 积分：1
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UART串口传输的Verilog RTL
uart串口传输的verilog RTL级源码，已通过仿真验证。文件主要包含发送、接受位处理，发送、接受字节帧处理，对学习串口通信的朋友很有帮助-uart serial transmission verilog RTL-level source code has been verified by simulation. File mainly contains the send, receive digital processing, sending, receiving bytes of frame processing, serial communications, a friend of learning helps
- 2022-01-28 20:31:09下载
- 积分：1
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UART
实现了UART的底层协议，加入了控制器，其波特率可以根据使用进行调整；发送模块、接收模块相互独立，互不影响。(Realization of the underlying protocol UART, joined the controller baud rate can be adjusted according to use transmission module, receiver module are independent of each other.)
- 2013-11-30 13:25:21下载
- 积分：1
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kalman_mppt-master
filter kalman mppt for PV
- 2020-10-04 13:27:39下载
- 积分：1
