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用数码管显示时间的数字电子钟verilog编写
用VERILOG编写的数字电子钟，用数码管进行显示时间-VERILOG prepared with digital electronic clock with a nixie tube display time
- 2022-06-22 05:51:35下载
- 积分：1
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code
代码文件夹：
ARVI_FSM.v为顶层文件，用于模拟时用。
dataHex.dat 为模拟输入文件（只有10行，象征的意思。实际我们模拟时，dataHex.dat文件足有1个多GB）
dataFormat.dat为输入文件对应的带格式的文件
使用modelsim模拟时，将dataHex.dat名字改为CPUContext.txt
结果:
result.txt
(Code folder: ARVI_FSM.v for top-level documents used for the simulation. dataHex.dat for analog input files (only 10 line, the meaning of the symbol. actual simulation we, dataHex.dat documents have more than one full GB) dataFormat.dat for the input file the corresponding file with modelsim simulation used to dataHex.dat name to CPUContext.txt results: result.txt)
- 2009-06-21 19:14:37下载
- 积分：1
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用vhdl来实现的数字频率合成的技术，几乎很全的，所有的都有...
用vhdl来实现的数字频率合成的技术，几乎很全的，所有的都有 -Use VHDL to realize the digital frequency synthesis technology, almost the whole of, all have
- 2022-02-04 17:07:58下载
- 积分：1
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zhinengchezaishipingxitong
设计了车载视频显示系统，设计了基于FPGA系统结构的车载视频显示电路板，利用FPGA显示视频控制，采集通道时许控制等。(The on-board video display system design, design the system structure based on FPGA video shows the circuit board, using the FPGA show video control, acquisition channel make control, etc
)
- 2011-12-08 15:37:21下载
- 积分：1
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延迟线模块的verilog代码，延迟线模块是数字电路设计常用的模块...
延迟线模块的verilog代码，延迟线模块是数字电路设计常用的模块-Delay-line module Verilog code, delay-line module is commonly used in digital circuit design module
- 2022-08-09 02:38:35下载
- 积分：1
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八路AD采集adc128s022
FPGA AD采集八路数据，12位分辨率，小梅哥FPGA的开发程序，实测可用(FPGA AD collects eight path data, 12 bit resolution, and the development program of Mayo FPGA.)
- 2020-12-17 16:59:11下载
- 积分：1
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这个程序是基于等精度测频原理的频率计，用VHDL语言实现，频率测量测量范围1~9999；用4位带小数点数码管显示其频率，并且具有超量程、欠量程提示功能。...
这个程序是基于等精度测频原理的频率计，用VHDL语言实现，频率测量测量范围1~9999；用4位带小数点数码管显示其频率，并且具有超量程、欠量程提示功能。-This procedure is based on the principle of frequency measurement accuracy, such as the frequency meter, using VHDL language, frequency measurement range 1 ~ 9999 with four decimal places with the frequency of the digital display and has a super-range, less range prompts.
- 2022-03-04 13:27:35下载
- 积分：1
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matlab-gmsk
基于matlab和vhdl的通信原理gmsk调制算法，主要包括GMSK相位路径的计算,GMSK眼图的仿真以验证相位计算的正确性,正余弦表的量化及bin文件的生成,以及用VHDL硬件语言所描述的基于EPM7128的地址逻辑.(Matlab and vhdl based on the principle gmsk Modulation of communication, including GMSK phase path calculation, GMSK eye diagrams of the simulation to verify the correctness of the phase calculation, is the cosine table generating quantitative and bin files, and using VHDL hardware description language logic based on the address of EPM7128.)
- 2020-12-19 10:39:10下载
- 积分：1
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xapp1161
多相滤波系统的设计与实现，有MATLAB仿真程序，有sysgen的系统仿真，还有VHDL代码，其中还有FIR的系数参数等等(Polyphase filter system, the design and implementation includes a MATLAB simulation program, sysgen system simulation, and VHDL code, including FIR coefficient parameters, and so on
)
- 2021-02-15 17:29:47下载
- 积分：1
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FIR_poroje
this project is about FIR FIlter By VHdl codes in the ISE.
- 2013-09-29 19:25:16下载
- 积分：1
