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VHDL_Tips
VHDL Coding style guide
- 2012-07-04 18:05:59下载
- 积分：1
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ioRWTest
C6000系列之6701开发板相关文件及说明(C6000 Series of 6701 development board-related documents and notes)
- 2008-04-17 17:08:58下载
- 积分：1
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this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer u...
this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering.
Here dataflow techniques and behavioural
-this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering.
Here dataflow techniques and behavioural
- 2022-05-22 09:03:05下载
- 积分：1
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SDH接收处理
模拟SDH帧结构，设计了状态机，能从连续传输的SDH字节流中找出帧头；从SDH字节流中，提取E2字节，并按照64K速率分别串行输出E2码流及时钟；设计了输入信号，输出包括E2串行数据、E2串行时钟和SDH帧头位置指示
- 2023-07-26 18:40:02下载
- 积分：1
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TCM解码，VHDL代码，是我在工作中做的工程代码，时序稳定，里面有syn以及软判决的算法，经典...
TCM解码，VHDL代码，是我在工作中做的工程代码，时序稳定，里面有syn以及软判决的算法，经典-TCM decoder, VHDL code, yes, I do work in the project code, timing stability, There are syn and soft-decision algorithm, classic!
- 2022-09-27 21:25:03下载
- 积分：1
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iic_sci
FPGA编程，经过团体奋战完成，全是底层的IIc和sci通信，完整版。(FPGA programming, after groups fight to the finish, all underlying SCI and IIc communication, full version)
- 2014-12-23 09:32:54下载
- 积分：1
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4bit-adder_verilog
4位全加法器的modelsim工程带testbench(Four full-adder modelsim project with testbench)
- 2020-08-16 16:38:25下载
- 积分：1
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本文件解压后clock_time.vhd采用编程环境maxplusII，完成时间秒定时、记时，设置时间秒、声光报警等功能。...
本文件解压后clock_time.vhd采用编程环境maxplusII，完成时间秒定时、记时，设置时间秒、声光报警等功能。-this document unpacked clock_time.vhd maxplusII use programming environment, the time for completion seconds timing, Hutchison, the set-up time seconds, sound, light, alarm functions.
- 2022-07-03 03:02:23下载
- 积分：1
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RLC Test
说明： RLC Test程序,一个电子竞赛的题目。里面有详尽的源代码。(RLC Test procedures, an electronic race issue. There are detailed source code.)
- 2005-09-04 20:58:18下载
- 积分：1
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基于CPLD的签到器的设计，用三维数组队人名进行储存
基于CPLD的签到器的设计，用三维数组队人名进行储存-Based on the attendance CPLD design, a few team names with three-dimensional storage
- 2023-01-07 09:45:04下载
- 积分：1
