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vhdl语言和verilog语言转换工具
能很容易的实现两种语言的相互转换...
vhdl语言和verilog语言转换工具
能很容易的实现两种语言的相互转换-verilog language vhdl language and conversion tools can easily achieve the conversion between two languages
- 2022-08-16 14:34:56下载
- 积分:1
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demo_as32ttl1w
说明: 可以获取各种字符,并在数码管显示出来,非常的靠谱且稳定(Various characters can be acquired and displayed on the digital tube.)
- 2020-06-16 15:00:02下载
- 积分:1
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xp2syscloclkpll
这个是讲pll的具体用法的,一般在fpga设计中都会用到 他,这个是lattice的xp2的pll的介绍,不过,fpga 都是相通的其他两家也差不多(Pll say this is the specific usage, the general design in the FPGA will use him, this is the lattice of the pll of xp2 introduction, however, fpga are connected to other two similar)
- 2007-10-31 21:03:07下载
- 积分:1
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FPGA UART的发送等
FPGA UART transmit and so on
- 2022-01-24 13:54:39下载
- 积分:1
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altfp_matrix_mult
浮点数 矩阵乘法模块 verilog语言编写 可直接调用(Floating-point matrix multiplication module can directly call verilog language)
- 2013-12-18 15:08:36下载
- 积分:1
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8051参考设计,和其他免费知识产权在8051相比,相对整个D。
8051参考设计,与其他8051的免费IP相比,文档相对较全,Oregano System 提供-8051 reference design, and other free IP in 8051 compared to relatively entire document, Oregano System for
- 2023-01-19 15:30:04下载
- 积分:1
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dianti
实现电梯的相关控制系统,在开发板EGO1上实现,数码管显示相关的楼层和状态(dianti in verilog)
- 2020-12-26 10:59:03下载
- 积分:1
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eeprom
实现I2C协议下EEPROM存储的数据读写控制(Under I2C protocol to achieve read and write data stored in EEPROM control)
- 2014-03-05 20:24:21下载
- 积分:1
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clock_gyc_system
基于用户自定义模块的实时时钟的设计;Qsys硬件设计;(Custom real-time clock module-based design Qsys hardware design )
- 2020-12-23 09:19:08下载
- 积分:1
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altfp_matrix_mult
浮点数 矩阵乘法模块 verilog语言编写 可直接调用(Floating-point matrix multiplication module can directly call verilog language)
- 2013-12-18 15:08:36下载
- 积分:1